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Searched refs:RegVT (Results 1 – 17 of 17) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DCallingConvLower.cpp258 for (MVT RegVT : RegParmTypes) { in analyzeMustTailForwardedRegisters() local
260 getRemainingRegParmsForType(RemainingRegs, RegVT, Fn); in analyzeMustTailForwardedRegisters()
262 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT); in analyzeMustTailForwardedRegisters()
265 Forwards.push_back(ForwardedRegister(VReg, PReg, RegVT)); in analyzeMustTailForwardedRegisters()
/freebsd-12.1/contrib/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp228 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
229 MVT::SimpleValueType SimpleTy = RegVT.getSimpleVT().SimpleTy; in LowerFormalArguments()
233 << RegVT.getEVTString() << '\n'; in LowerFormalArguments()
242 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerFormalArguments()
247 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
250 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
/freebsd-12.1/contrib/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1071 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
1073 if (RegVT == MVT::i8) { in LowerFormalArguments()
1075 } else if (RegVT == MVT::i16) { in LowerFormalArguments()
1082 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); in LowerFormalArguments()
1099 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
1104 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
1200 EVT RegVT = VA.getLocVT(); in LowerCall() local
1210 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); in LowerCall()
1213 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); in LowerCall()
1216 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp486 EVT RegVT = VA.getLocVT(); in LowerCallArguments() local
487 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCallArguments()
490 << (unsigned)RegVT.getSimpleVT().SimpleTy << "\n"); in LowerCallArguments()
496 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCallArguments()
/freebsd-12.1/contrib/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp460 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
461 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
465 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerCCCArguments()
471 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerCCCArguments()
474 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerCCCArguments()
485 << RegVT.getEVTString() << "\n"); in LowerCCCArguments()
/freebsd-12.1/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp625 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
626 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
631 << RegVT.getEVTString() << "\n"; in LowerCCCArguments()
638 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
644 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerCCCArguments()
647 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerCCCArguments()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp734 MVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
736 RegVT = VA.getValVT(); in LowerFormalArguments()
738 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
740 SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerFormalArguments()
746 assert(RegVT.getSizeInBits() <= 32); in LowerFormalArguments()
747 SDValue T = DAG.getNode(ISD::AND, dl, RegVT, in LowerFormalArguments()
748 Copy, DAG.getConstant(1, dl, RegVT)); in LowerFormalArguments()
749 Copy = DAG.getSetCC(dl, MVT::i1, T, DAG.getConstant(0, dl, RegVT), in LowerFormalArguments()
753 unsigned RegSize = RegVT.getSizeInBits(); in LowerFormalArguments()
755 Subtarget.isHVXVectorType(RegVT)); in LowerFormalArguments()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.h308 MVT RegVT; member
321 RegVT(RgVT), Emitted(E), ContiguousRange(CR), Parent(P), Default(D), in BitTestBlock()
H A DTargetLowering.cpp4787 EVT RegVT = Value.getValueType(); in scalarizeVectorStore() local
4788 EVT RegSclVT = RegVT.getScalarType(); in scalarizeVectorStore()
4888 MVT RegVT = getRegisterType(*DAG.getContext(), intVT); in expandUnalignedLoad() local
4890 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedLoad()
4894 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); in expandUnalignedLoad()
4928 DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, in expandUnalignedLoad()
5040 MVT RegVT = in expandUnalignedStore() local
5046 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedStore()
5050 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); in expandUnalignedStore()
5069 RegVT, dl, Store, StackPtr, in expandUnalignedStore()
[all …]
H A DSelectionDAGBuilder.cpp2382 B.RegVT = VT.getSimpleVT(); in visitBitTestHeader()
2383 B.Reg = FuncInfo.CreateReg(B.RegVT); in visitBitTestHeader()
2412 MVT VT = BB.RegVT; in visitBitTestCase()
7371 const MVT RegVT = *TRI.legalclasstypes_begin(*RC); in GetRegistersForValue() local
7387 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { in GetRegistersForValue()
7393 DAG.getNode(ISD::BITCAST, DL, RegVT, OpInfo.CallOperand); in GetRegistersForValue()
7394 OpInfo.ConstraintVT = RegVT; in GetRegistersForValue()
7415 ValueVT = RegVT; in GetRegistersForValue()
7444 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); in GetRegistersForValue()
7740 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType(); in visitInlineAsm() local
[all …]
H A DLegalizeIntegerTypes.cpp983 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT); in PromoteIntRes_VAARG() local
989 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2), in PromoteIntRes_VAARG()
1005 DAG.getConstant(i * RegVT.getSizeInBits(), dl, in PromoteIntRes_VAARG()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp3443 MVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
3445 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
3450 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); in LowerFormalArguments()
3456 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || in LowerFormalArguments()
3457 (RegVT == MVT::i64 && ValVT == MVT::f64) || in LowerFormalArguments()
3458 (RegVT == MVT::f64 && ValVT == MVT::i64)) in LowerFormalArguments()
3460 else if (ABI.IsO32() && RegVT == MVT::i32 && in LowerFormalArguments()
3464 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); in LowerFormalArguments()
/freebsd-12.1/contrib/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1295 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
1296 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
1301 << RegVT.getEVTString() << "\n"; in LowerCCCArguments()
1308 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp610 EVT RegVT = ST->getValue().getValueType(); in tryTLSXFormStore() local
617 Opcode = (RegVT == MVT::i32) ? PPC::STBXTLS_32 : PPC::STBXTLS; in tryTLSXFormStore()
621 Opcode = (RegVT == MVT::i32) ? PPC::STHXTLS_32 : PPC::STHXTLS; in tryTLSXFormStore()
625 Opcode = (RegVT == MVT::i32) ? PPC::STWXTLS_32 : PPC::STWXTLS; in tryTLSXFormStore()
653 EVT RegVT = LD->getValueType(0); in tryTLSXFormLoad() local
659 Opcode = (RegVT == MVT::i32) ? PPC::LBZXTLS_32 : PPC::LBZXTLS; in tryTLSXFormLoad()
663 Opcode = (RegVT == MVT::i32) ? PPC::LHZXTLS_32 : PPC::LHZXTLS; in tryTLSXFormLoad()
667 Opcode = (RegVT == MVT::i32) ? PPC::LWZXTLS_32 : PPC::LWZXTLS; in tryTLSXFormLoad()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp3205 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
3217 if (RegVT == MVT::i8) in LowerFormalArguments()
3219 else if (RegVT == MVT::i16) in LowerFormalArguments()
3221 else if (RegVT == MVT::i32) in LowerFormalArguments()
3225 else if (RegVT == MVT::f32) in LowerFormalArguments()
3227 else if (RegVT == MVT::f64) in LowerFormalArguments()
3229 else if (RegVT == MVT::f80) in LowerFormalArguments()
3231 else if (RegVT == MVT::f128) in LowerFormalArguments()
3241 else if (RegVT == MVT::v1i1) in LowerFormalArguments()
3743 EVT RegVT = VA.getLocVT(); in LowerCall() local
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp3079 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
3084 if (RegVT == MVT::i32) in LowerFormalArguments()
3086 else if (RegVT == MVT::i64) in LowerFormalArguments()
3088 else if (RegVT == MVT::f16) in LowerFormalArguments()
3090 else if (RegVT == MVT::f32) in LowerFormalArguments()
3092 else if (RegVT == MVT::f64 || RegVT.is64BitVector()) in LowerFormalArguments()
3094 else if (RegVT == MVT::f128 || RegVT.is128BitVector()) in LowerFormalArguments()
3101 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); in LowerFormalArguments()
3119 assert(RegVT == Ins[i].VT && "incorrect register location selected"); in LowerFormalArguments()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp2379 EVT RegVT = VA.getLocVT(); in IsEligibleForTailCallOptimization() local
2393 if (RegVT == MVT::v2f64) { in IsEligibleForTailCallOptimization()
3670 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
3703 if (RegVT == MVT::f16) in LowerFormalArguments()
3705 else if (RegVT == MVT::f32) in LowerFormalArguments()
3707 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16) in LowerFormalArguments()
3709 else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16) in LowerFormalArguments()
3711 else if (RegVT == MVT::i32) in LowerFormalArguments()
3719 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); in LowerFormalArguments()
3732 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
[all …]