Lines Matching refs:RegVT
3205 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
3217 if (RegVT == MVT::i8) in LowerFormalArguments()
3219 else if (RegVT == MVT::i16) in LowerFormalArguments()
3221 else if (RegVT == MVT::i32) in LowerFormalArguments()
3223 else if (Is64Bit && RegVT == MVT::i64) in LowerFormalArguments()
3225 else if (RegVT == MVT::f32) in LowerFormalArguments()
3227 else if (RegVT == MVT::f64) in LowerFormalArguments()
3229 else if (RegVT == MVT::f80) in LowerFormalArguments()
3231 else if (RegVT == MVT::f128) in LowerFormalArguments()
3233 else if (RegVT.is512BitVector()) in LowerFormalArguments()
3235 else if (RegVT.is256BitVector()) in LowerFormalArguments()
3237 else if (RegVT.is128BitVector()) in LowerFormalArguments()
3239 else if (RegVT == MVT::x86mmx) in LowerFormalArguments()
3241 else if (RegVT == MVT::v1i1) in LowerFormalArguments()
3243 else if (RegVT == MVT::v8i1) in LowerFormalArguments()
3245 else if (RegVT == MVT::v16i1) in LowerFormalArguments()
3247 else if (RegVT == MVT::v32i1) in LowerFormalArguments()
3249 else if (RegVT == MVT::v64i1) in LowerFormalArguments()
3255 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); in LowerFormalArguments()
3262 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
3265 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
3272 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1) in LowerFormalArguments()
3279 ArgValue = lowerRegToMasks(ArgValue, VA.getValVT(), RegVT, dl, DAG); in LowerFormalArguments()
3743 EVT RegVT = VA.getLocVT(); in LowerCall() local
3752 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); in LowerCall()
3755 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); in LowerCall()
3760 Arg = lowerMasksToReg(Arg, RegVT, dl, DAG); in LowerCall()
3761 else if (RegVT.is128BitVector()) { in LowerCall()
3767 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); in LowerCall()
3770 Arg = DAG.getBitcast(RegVT, Arg); in LowerCall()
20527 MVT RegVT = Op.getSimpleValueType(); in LowerLoad() local
20528 assert(RegVT.isVector() && "We only custom lower vector loads."); in LowerLoad()
20529 assert(RegVT.isInteger() && in LowerLoad()
20537 if (RegVT.getVectorElementType() == MVT::i1) { in LowerLoad()
20538 assert(EVT(RegVT) == MemVT && "Expected non-extending load"); in LowerLoad()
20539 assert(RegVT.getVectorNumElements() <= 8 && "Unexpected VT"); in LowerLoad()
20551 Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, RegVT, in LowerLoad()
20561 unsigned RegSz = RegVT.getSizeInBits(); in LowerLoad()
20567 assert(MemVT != RegVT && "Cannot extend to the same type"); in LowerLoad()
20570 unsigned NumElems = RegVT.getVectorNumElements(); in LowerLoad()
20600 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2); in LowerLoad()
20612 SDValue SExt = DAG.getSExtOrTrunc(Load, dl, RegVT); in LowerLoad()
20647 if (Ext == ISD::EXTLOAD && !Subtarget.hasBWI() && RegVT == MVT::v8i64 && in LowerLoad()
20706 SDValue Sext = getExtendInVec(/*Signed*/true, dl, RegVT, SlicedVec, DAG); in LowerLoad()
20710 if (Ext == ISD::EXTLOAD && !Subtarget.hasBWI() && RegVT == MVT::v8i64 && in LowerLoad()
20712 SDValue Sext = getExtendInVec(/*Signed*/false, dl, RegVT, SlicedVec, DAG); in LowerLoad()
20725 Shuff = DAG.getBitcast(RegVT, Shuff); in LowerLoad()
37250 EVT RegVT = Ld->getValueType(0); in combineLoad() local
37262 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() && in combineLoad()
37265 (TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT, in combineLoad()
37267 unsigned NumElems = RegVT.getVectorNumElements(); in combineLoad()
37288 SDValue NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Load1, Load2); in combineLoad()