Lines Matching refs:RegVT
1071 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
1073 if (RegVT == MVT::i8) { in LowerFormalArguments()
1075 } else if (RegVT == MVT::i16) { in LowerFormalArguments()
1082 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); in LowerFormalArguments()
1099 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
1104 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
1200 EVT RegVT = VA.getLocVT(); in LowerCall() local
1210 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); in LowerCall()
1213 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); in LowerCall()
1216 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall()
1219 Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg); in LowerCall()