Lines Matching refs:RegVT
2382 B.RegVT = VT.getSimpleVT(); in visitBitTestHeader()
2383 B.Reg = FuncInfo.CreateReg(B.RegVT); in visitBitTestHeader()
2412 MVT VT = BB.RegVT; in visitBitTestCase()
7371 const MVT RegVT = *TRI.legalclasstypes_begin(*RC); in GetRegistersForValue() local
7387 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { in GetRegistersForValue()
7393 DAG.getNode(ISD::BITCAST, DL, RegVT, OpInfo.CallOperand); in GetRegistersForValue()
7394 OpInfo.ConstraintVT = RegVT; in GetRegistersForValue()
7398 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { in GetRegistersForValue()
7415 ValueVT = RegVT; in GetRegistersForValue()
7444 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); in GetRegistersForValue()
7740 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType(); in visitInlineAsm() local
7743 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT)) { in visitInlineAsm()
7755 RegsForValue MatchedRegs(Regs, RegVT, InOperandVal.getValueType()); in visitInlineAsm()
9159 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT); in LowerArguments() local
9161 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, RegVT, VT, in LowerArguments()
9166 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT)); in LowerArguments()