| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | AllocationOrder.cpp | 32 const RegisterClassInfo &RegClassInfo, in AllocationOrder() argument
37 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in AllocationOrder()
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| H A D | BreakFalseDeps.cpp | 39 RegisterClassInfo RegClassInfo; member in llvm::BreakFalseDeps
145 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef()
261 RegClassInfo.runOnMachineFunction(mf); in runOnMachineFunction()
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| H A D | RegAllocBase.cpp | 66 RegClassInfo.runOnMachineFunction(vrm.getMachineFunction()); in init()
134 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front()); in allocatePhysRegs()
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| H A D | AllocationOrder.h | 46 const RegisterClassInfo &RegClassInfo,
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| H A D | RegAllocBase.h | 70 RegisterClassInfo RegClassInfo; variable
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| H A D | CriticalAntiDepBreaker.h | 42 const RegisterClassInfo &RegClassInfo; variable
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| H A D | PostRASchedulerList.cpp | 82 RegisterClassInfo RegClassInfo; member in __anon0a44832d0111::PostRAScheduler
291 RegClassInfo.runOnMachineFunction(Fn); in runOnMachineFunction()
314 SchedulePostRATDList Scheduler(Fn, MLI, AA, RegClassInfo, AntiDepMode, in runOnMachineFunction()
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| H A D | RegAllocGreedy.cpp | 806 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix); in canReassign()
910 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) < in canEvictInterference()
911 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg))); in canEvictInterference()
1083 unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg); in isUnusedCalleeSavedReg()
1115 unsigned MinCost = RegClassInfo.getMinCost(RC); in tryEvict()
1125 OrderLimit = RegClassInfo.getLastCostChange(RC); in tryEvict()
1140 << printReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI) in tryEvict()
1676 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)); in splitAroundRegion()
2009 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)); in tryBlockSplit()
2076 if (!RegClassInfo.isProperSubClass(CurRC)) in tryInstructionSplit()
[all …]
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| H A D | AggressiveAntiDepBreaker.h | 123 const RegisterClassInfo &RegClassInfo; variable
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| H A D | CriticalAntiDepBreaker.cpp | 49 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI), in CriticalAntiDepBreaker()
398 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); in findSuitableFreeRegister()
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| H A D | MachineScheduler.cpp | 142 RegClassInfo = new RegisterClassInfo(); in MachineSchedContext()
146 delete RegClassInfo; in ~MachineSchedContext()
384 RegClassInfo->runOnMachineFunction(*MF); in runOnMachineFunction()
1012 TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin, in initRegPressure()
1014 BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd, in initRegPressure()
1066 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i); in initRegPressure()
1096 unsigned Limit = RegClassInfo->getRegPressureSetLimit(ID); in updateScheduledPressure()
1281 RPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd, in buildDAGWithRegPressure()
2730 unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs( in initPolicy()
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| H A D | RegAllocBasic.cpp | 263 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix); in selectOrSplit()
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| H A D | RegAllocFast.cpp | 75 RegisterClassInfo RegClassInfo; member in __anon233ffc900111::RegAllocFast
586 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtReg()
1112 RegClassInfo.runOnMachineFunction(MF); in runOnMachineFunction()
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| H A D | AggressiveAntiDepBreaker.cpp | 131 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI) { in AggressiveAntiDepBreaker()
633 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
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| H A D | TargetRegisterInfo.cpp | 48 const RegClassInfo *const RCIs, in TargetRegisterInfo()
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| H A D | RegisterCoalescer.cpp | 119 RegisterClassInfo RegClassInfo; member in __anone68f6e4f0111::RegisterCoalescer
1887 if (!CP.isPhys() && RegClassInfo.isProperSubClass(CP.getNewRC())) in joinCopy()
3650 RegClassInfo.runOnMachineFunction(fn); in runOnMachineFunction()
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| H A D | MachinePipeliner.cpp | 187 RegClassInfo.runOnMachineFunction(*MF); in INITIALIZE_PASS_DEPENDENCY()
289 SwingSchedulerDAG SMS(*this, L, getAnalysis<LiveIntervals>(), RegClassInfo); in swingModuloScheduler()
1374 RecRPTracker.init(&MF, &RegClassInfo, &LIS, BB, BB->end(), false, true); in registerPressureFilter()
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 224 struct RegClassInfo { struct
236 const RegClassInfo *const RCInfos; argument
246 const RegClassInfo *const RCIs,
678 const RegClassInfo &getRegClassInfo(const TargetRegisterClass &RC) const { in getRegClassInfo()
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| H A D | MachineScheduler.h | 127 RegisterClassInfo *RegClassInfo; member
398 RegisterClassInfo *RegClassInfo;
442 RegClassInfo(C->RegClassInfo), RPTracker(RegPressure), in ScheduleDAGMILive()
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| H A D | MachinePipeliner.h | 65 RegisterClassInfo RegClassInfo; variable
115 const RegisterClassInfo &RegClassInfo; variable
195 RegClassInfo(rci), Topo(SUnits, &ExitSU) { in SwingSchedulerDAG()
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonMachineScheduler.h | 100 RegisterClassInfo *getRegClassInfo() { return RegClassInfo; } in getRegClassInfo()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | GCNSchedStrategy.cpp | 44 SGPRExcessLimit = Context->RegClassInfo in initialize()
46 VGPRExcessLimit = Context->RegClassInfo in initialize()
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| H A D | SIMachineScheduler.h | 453 RPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin, false, false); in initRPTracker()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIRParser.cpp | 875 auto RegClassInfo = Names2RegClasses.find(Name); in getRegClass() local
876 if (RegClassInfo == Names2RegClasses.end()) in getRegClass()
878 return RegClassInfo->getValue(); in getRegClass()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 110 RegisterClassInfo RegClassInfo; member
582 RegClassInfo.runOnMachineFunction(*MF); in findFreeReg()
586 for (unsigned Reg : RegClassInfo.getOrder(&RegClass)) in findFreeReg()
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