12754fe60SDimitry Andric //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
22754fe60SDimitry Andric //
32754fe60SDimitry Andric //                     The LLVM Compiler Infrastructure
42754fe60SDimitry Andric //
52754fe60SDimitry Andric // This file is distributed under the University of Illinois Open Source
62754fe60SDimitry Andric // License. See LICENSE.TXT for details.
72754fe60SDimitry Andric //
82754fe60SDimitry Andric //===----------------------------------------------------------------------===//
92754fe60SDimitry Andric //
102754fe60SDimitry Andric // This file implements an allocation order for virtual registers.
112754fe60SDimitry Andric //
122754fe60SDimitry Andric // The preferred allocation order for a virtual register depends on allocation
132754fe60SDimitry Andric // hints and target hooks. The AllocationOrder class encapsulates all of that.
142754fe60SDimitry Andric //
152754fe60SDimitry Andric //===----------------------------------------------------------------------===//
162754fe60SDimitry Andric 
172754fe60SDimitry Andric #include "AllocationOrder.h"
18139f7f9bSDimitry Andric #include "llvm/CodeGen/MachineFunction.h"
192754fe60SDimitry Andric #include "llvm/CodeGen/MachineRegisterInfo.h"
207ae0e2c9SDimitry Andric #include "llvm/CodeGen/RegisterClassInfo.h"
21139f7f9bSDimitry Andric #include "llvm/CodeGen/VirtRegMap.h"
22139f7f9bSDimitry Andric #include "llvm/Support/Debug.h"
23139f7f9bSDimitry Andric #include "llvm/Support/raw_ostream.h"
242754fe60SDimitry Andric 
252754fe60SDimitry Andric using namespace llvm;
262754fe60SDimitry Andric 
2791bc56edSDimitry Andric #define DEBUG_TYPE "regalloc"
2891bc56edSDimitry Andric 
292754fe60SDimitry Andric // Compare VirtRegMap::getRegAllocPref().
AllocationOrder(unsigned VirtReg,const VirtRegMap & VRM,const RegisterClassInfo & RegClassInfo,const LiveRegMatrix * Matrix)302754fe60SDimitry Andric AllocationOrder::AllocationOrder(unsigned VirtReg,
312754fe60SDimitry Andric                                  const VirtRegMap &VRM,
327d523365SDimitry Andric                                  const RegisterClassInfo &RegClassInfo,
337d523365SDimitry Andric                                  const LiveRegMatrix *Matrix)
342cab237bSDimitry Andric   : Pos(0), HardHints(false) {
35139f7f9bSDimitry Andric   const MachineFunction &MF = VRM.getMachineFunction();
36139f7f9bSDimitry Andric   const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
37139f7f9bSDimitry Andric   Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
382cab237bSDimitry Andric   if (TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix))
392cab237bSDimitry Andric     HardHints = true;
40139f7f9bSDimitry Andric   rewind();
412754fe60SDimitry Andric 
42*4ba319b5SDimitry Andric   LLVM_DEBUG({
43139f7f9bSDimitry Andric     if (!Hints.empty()) {
44139f7f9bSDimitry Andric       dbgs() << "hints:";
45139f7f9bSDimitry Andric       for (unsigned I = 0, E = Hints.size(); I != E; ++I)
462cab237bSDimitry Andric         dbgs() << ' ' << printReg(Hints[I], TRI);
47139f7f9bSDimitry Andric       dbgs() << '\n';
48bd5abe19SDimitry Andric     }
49139f7f9bSDimitry Andric   });
50139f7f9bSDimitry Andric #ifndef NDEBUG
51139f7f9bSDimitry Andric   for (unsigned I = 0, E = Hints.size(); I != E; ++I)
52d88c1a5aSDimitry Andric     assert(is_contained(Order, Hints[I]) &&
53139f7f9bSDimitry Andric            "Target hint is outside allocation order.");
54139f7f9bSDimitry Andric #endif
552754fe60SDimitry Andric }
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