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Searched refs:PredReg (Results 1 – 24 of 24) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp554 .addReg(PredReg); in UpdateBaseRegUses()
575 .addReg(PredReg); in UpdateBaseRegUses()
892 unsigned PredReg = 0; in MergeOpsUpdate() local
1194 MIPredReg != PredReg) in isIncrementOrDecrement()
1259 unsigned PredReg = 0; in MergeBaseUpdateLSMultiple() local
1313 .addImm(Pred).addReg(PredReg); in MergeBaseUpdateLSMultiple()
1401 unsigned PredReg = 0; in MergeBaseUpdateLoadStore() local
1508 unsigned PredReg; in MergeBaseUpdateLSDouble() local
1666 unsigned PredReg = 0; in FixInvalidRegPairOp() local
1761 unsigned PredReg = 0; in LoadStoreMultipleOpti() local
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H A DThumb2InstrInfo.cpp70 unsigned PredReg = 0; in ReplaceTailWithBranchTo() local
71 ARMCC::CondCodes CC = getInstrPredicate(*Tail, PredReg); in ReplaceTailWithBranchTo()
118 unsigned PredReg = 0; in isLegalToSplitMBBAt() local
119 return getITInstrPredicate(*MBBI, PredReg) == ARMCC::AL; in isLegalToSplitMBBAt()
242 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
259 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
275 .add(predOps(Pred, PredReg)) in emitT2RegPlusImmediate()
287 .add(predOps(Pred, PredReg)) in emitT2RegPlusImmediate()
487 unsigned PredReg; in rewriteT2FrameIndex() local
675 unsigned &PredReg) { in getITInstrPredicate() argument
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H A DThumb2SizeReduction.cpp472 unsigned PredReg = MI->getOperand(5).getReg(); in ReduceLoadStore() local
485 .addReg(PredReg) in ReduceLoadStore()
680 unsigned PredReg = 0; in ReduceSpecial() local
681 if (getInstrPredicate(*MI, PredReg) == ARMCC::AL) { in ReduceSpecial()
722 unsigned PredReg = 0; in ReduceSpecial() local
724 if (getInstrPredicate(*MI, PredReg) != ARMCC::AL) in ReduceSpecial()
793 unsigned PredReg = 0; in ReduceTo2Addr() local
794 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in ReduceTo2Addr()
886 unsigned PredReg = 0; in ReduceToNarrow() local
887 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in ReduceToNarrow()
H A DARMBaseInstrInfo.h456 unsigned PredReg = 0) {
458 MachineOperand::CreateReg(PredReg, false)}};
511 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg);
533 ARMCC::CondCodes Pred, unsigned PredReg,
540 ARMCC::CondCodes Pred, unsigned PredReg,
H A DThumbRegisterInfo.cpp66 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb1LoadConstPool() argument
78 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg) in emitThumb1LoadConstPool()
86 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb2LoadConstPool() argument
107 ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool() argument
114 PredReg, MIFlags); in emitLoadConstPool()
117 PredReg, MIFlags); in emitLoadConstPool()
H A DMLxExpansionPass.cpp285 unsigned PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction() local
298 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
310 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
H A DARMBaseRegisterInfo.cpp443 ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool() argument
455 .add(predOps(Pred, PredReg)) in emitLoadConstPool()
788 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); in eliminateFrameIndex() local
796 Offset, Pred, PredReg, TII); in eliminateFrameIndex()
800 Offset, Pred, PredReg, TII); in eliminateFrameIndex()
H A DThumbRegisterInfo.h44 unsigned PredReg = 0,
H A DThumb2InstrInfo.h71 ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, unsigned &PredReg);
H A DThumb2ITBlockPass.cpp206 unsigned PredReg = 0; in InsertITInstructions() local
207 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg); in InsertITInstructions()
H A DARMBaseRegisterInfo.h189 unsigned PredReg = 0,
H A DARMConstantIslandPass.cpp1417 unsigned PredReg = 0; in createNewWater() local
1418 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg); in createNewWater()
1440 LLVM_DEBUG(unsigned PredReg; assert( in createNewWater()
1441 !isThumb || getITInstrPredicate(*MI, PredReg) == ARMCC::AL)); in createNewWater()
1890 unsigned PredReg = 0; in optimizeThumb2Branches() local
1891 ARMCC::CondCodes Pred = getInstrPredicate(*Br.MI, PredReg); in optimizeThumb2Branches()
1909 Pred = getInstrPredicate(*CmpMI, PredReg); in optimizeThumb2Branches()
H A DARMFrameLowering.cpp170 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { in emitRegPlusImmediate() argument
173 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
176 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
184 unsigned PredReg = 0) { in emitSPUpdate() argument
186 MIFlags, Pred, PredReg); in emitSPUpdate()
2062 unsigned PredReg = TII.getFramePred(Old); in eliminateCallFramePseudoInstr() local
2065 Pred, PredReg); in eliminateCallFramePseudoInstr()
2069 Pred, PredReg); in eliminateCallFramePseudoInstr()
H A DARMBaseInstrInfo.cpp1912 unsigned PredReg = 0; in isProfitableToIfCvt() local
1913 ARMCC::CondCodes P = getInstrPredicate(*CmpMI, PredReg); in isProfitableToIfCvt()
1993 unsigned &PredReg) { in getInstrPredicate() argument
1996 PredReg = 0; in getInstrPredicate()
2000 PredReg = MI.getOperand(PIdx+1).getReg(); in getInstrPredicate()
2023 unsigned PredReg = 0; in commuteInstructionImpl() local
2024 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); in commuteInstructionImpl()
2026 if (CC == ARMCC::AL || PredReg != ARM::CPSR) in commuteInstructionImpl()
2227 ARMCC::CondCodes Pred, unsigned PredReg, in emitARMRegPlusImmediate() argument
2233 .add(predOps(Pred, PredReg)) in emitARMRegPlusImmediate()
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H A DARMExpandPseudoInsts.cpp825 unsigned PredReg = 0; in ExpandMOV32BitImm() local
826 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in ExpandMOV32BitImm()
853 LO16.addImm(Pred).addReg(PredReg).add(condCodeOp()); in ExpandMOV32BitImm()
854 HI16.addImm(Pred).addReg(PredReg).add(condCodeOp()); in ExpandMOV32BitImm()
904 LO16.addImm(Pred).addReg(PredReg); in ExpandMOV32BitImm()
905 HI16.addImm(Pred).addReg(PredReg); in ExpandMOV32BitImm()
H A DARMISelDAGToDAG.cpp3045 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
3046 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select()
3068 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
3069 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select()
3090 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
3091 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCompound.cpp178 unsigned PredReg = Predicate.getReg(); in getCompoundOp() local
180 assert((PredReg == Hexagon::P0) || (PredReg == Hexagon::P1) || in getCompoundOp()
181 (PredReg == Hexagon::P2) || (PredReg == Hexagon::P3)); in getCompoundOp()
188 return (PredReg == Hexagon::P0) ? fp0_jump_nt : fp1_jump_nt; in getCompoundOp()
190 return (PredReg == Hexagon::P0) ? fp0_jump_t : fp1_jump_t; in getCompoundOp()
192 return (PredReg == Hexagon::P0) ? tp0_jump_nt : tp1_jump_nt; in getCompoundOp()
194 return (PredReg == Hexagon::P0) ? tp0_jump_t : tp1_jump_t; in getCompoundOp()
H A DHexagonMCChecker.cpp68 void HexagonMCChecker::initReg(MCInst const &MCI, unsigned R, unsigned &PredReg, in initReg() argument
72 PredReg = R; in initReg()
77 NewPreds.insert(PredReg); in initReg()
90 unsigned PredReg = Hexagon::NoRegister; in init() local
96 initReg(MCI, MCI.getOperand(i).getReg(), PredReg, isTrue); in init()
98 initReg(MCI, MCID.getImplicitUses()[i], PredReg, isTrue); in init()
126 Defs[R].insert(PredSense(PredReg, isTrue)); in init()
178 Defs[*SRI].insert(PredSense(PredReg, isTrue)); in init()
H A DHexagonMCChecker.h78 void initReg(MCInst const &, unsigned, unsigned &PredReg, bool &isTrue);
H A DHexagonMCDuplexInfo.cpp192 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
480 PredReg = MCI.getOperand(1).getReg(); // P0 in getDuplexCandidateGroup()
482 Hexagon::P0 == PredReg && minConstant(MCI, 2) == 0) { in getDuplexCandidateGroup()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonGenPredicate.cpp118 bool isScalarPred(Register PredReg);
320 bool HexagonGenPredicate::isScalarPred(Register PredReg) { in isScalarPred() argument
322 WorkQ.push(PredReg); in isScalarPred()
H A DHexagonInstrInfo.h434 bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const;
467 bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
H A DHexagonInstrInfo.cpp1548 unsigned PredReg, PredRegPos, PredRegFlags; in PredicateInstruction() local
1549 bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags); in PredicateInstruction()
1552 T.addReg(PredReg, PredRegFlags); in PredicateInstruction()
1566 MRI.clearKillFlags(PredReg); in PredicateInstruction()
3053 unsigned PredReg) const { in predCanBeUsedAsDotNew()
3056 if (MO.isRegMask() && MO.clobbersPhysReg(PredReg)) in predCanBeUsedAsDotNew()
3058 if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg)) in predCanBeUsedAsDotNew()
4217 unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const { in getPredReg() argument
4225 PredReg = Cond[1].getReg(); in getPredReg()
H A DHexagonHardwareLoops.cpp648 unsigned PredReg, PredPos, PredRegFlags; in getLoopTripCount() local
649 if (!TII->getPredReg(Cond, PredReg, PredPos, PredRegFlags)) in getLoopTripCount()
651 MachineInstr *CondI = MRI->getVRegDef(PredReg); in getLoopTripCount()