172                            ARMCC::CondCodes Pred, unsigned PredReg);
176         ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
181         ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
485                                         unsigned PredReg) {  in UpdateBaseRegUses()  argument
554           .addReg(PredReg);  in UpdateBaseRegUses()
575         .addReg(PredReg);  in UpdateBaseRegUses()
625     ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,  in CreateLoadStoreMulti()  argument
739               .add(predOps(Pred, PredReg));  in CreateLoadStoreMulti()
750             .add(predOps(Pred, PredReg));  in CreateLoadStoreMulti()
756             .add(predOps(Pred, PredReg));  in CreateLoadStoreMulti()
761           .add(predOps(Pred, PredReg))  in CreateLoadStoreMulti()
806       UpdateBaseRegUses(MBB, InsertBefore, DL, Base, NumRegs, Pred, PredReg);  in CreateLoadStoreMulti()
813   MIB.addImm(Pred).addReg(PredReg);  in CreateLoadStoreMulti()
824     ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,  in CreateLoadStoreDouble()  argument
840   MIB.addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);  in CreateLoadStoreDouble()
892   unsigned PredReg = 0;  in MergeOpsUpdate()  local
893   ARMCC::CondCodes Pred = getInstrPredicate(*First, PredReg);  in MergeOpsUpdate()
898                                    Opcode, Pred, PredReg, DL, Regs);  in MergeOpsUpdate()
901                                   Opcode, Pred, PredReg, DL, Regs);  in MergeOpsUpdate()
1175                                   ARMCC::CondCodes Pred, unsigned PredReg) {  in isIncrementOrDecrement()  argument
1194       MIPredReg != PredReg)  in isIncrementOrDecrement()
1205                  ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) {  in findIncDecBefore()  argument
1218   Offset = isIncrementOrDecrement(*PrevMBBI, Reg, Pred, PredReg);  in findIncDecBefore()
1225                 ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) {  in findIncDecAfter()  argument
1236   Offset = isIncrementOrDecrement(*NextMBBI, Reg, Pred, PredReg);  in findIncDecAfter()
1259   unsigned PredReg = 0;  in MergeBaseUpdateLSMultiple()  local
1260   ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);  in MergeBaseUpdateLSMultiple()
1275     = findIncDecBefore(MBBI, Base, Pred, PredReg, Offset);  in MergeBaseUpdateLSMultiple()
1282     MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset);  in MergeBaseUpdateLSMultiple()
1313     .addImm(Pred).addReg(PredReg);  in MergeBaseUpdateLSMultiple()
1401   unsigned PredReg = 0;  in MergeBaseUpdateLoadStore()  local
1402   ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);  in MergeBaseUpdateLoadStore()
1408     = findIncDecBefore(MBBI, Base, Pred, PredReg, Offset);  in MergeBaseUpdateLoadStore()
1415     MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset);  in MergeBaseUpdateLoadStore()
1437       .addImm(Pred).addReg(PredReg)  in MergeBaseUpdateLoadStore()
1446           .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);  in MergeBaseUpdateLoadStore()
1454             .add(predOps(Pred, PredReg));  in MergeBaseUpdateLoadStore()
1462           .add(predOps(Pred, PredReg));  in MergeBaseUpdateLoadStore()
1477           .add(predOps(Pred, PredReg));  in MergeBaseUpdateLoadStore()
1484           .add(predOps(Pred, PredReg));  in MergeBaseUpdateLoadStore()
1508   unsigned PredReg;  in MergeBaseUpdateLSDouble()  local
1509   ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);  in MergeBaseUpdateLSDouble()
1514                                                             PredReg, Offset);  in MergeBaseUpdateLSDouble()
1519     MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset);  in MergeBaseUpdateLSDouble()
1536      .addImm(Offset).addImm(Pred).addReg(PredReg);  in MergeBaseUpdateLSDouble()
1610                           unsigned PredReg, const TargetInstrInfo *TII) {  in InsertLDR_STR()  argument
1616     MIB.addImm(Offset).addImm(Pred).addReg(PredReg);  in InsertLDR_STR()
1622     MIB.addImm(Offset).addImm(Pred).addReg(PredReg);  in InsertLDR_STR()
1666   unsigned PredReg = 0;  in FixInvalidRegPairOp()  local
1667   ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);  in FixInvalidRegPairOp()
1678         .addImm(Pred).addReg(PredReg)  in FixInvalidRegPairOp()
1685         .addImm(Pred).addReg(PredReg)  in FixInvalidRegPairOp()
1707                     false, BaseReg, false, BaseUndef, Pred, PredReg, TII);  in FixInvalidRegPairOp()
1709                     false, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII);  in FixInvalidRegPairOp()
1722                     EvenUndef, BaseReg, false, BaseUndef, Pred, PredReg, TII);  in FixInvalidRegPairOp()
1724                     OddUndef, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII);  in FixInvalidRegPairOp()
1761       unsigned PredReg = 0;  in LoadStoreMultipleOpti()  local
1762       ARMCC::CondCodes Pred = getInstrPredicate(*MBBI, PredReg);  in LoadStoreMultipleOpti()
2035                           unsigned &PredReg, ARMCC::CondCodes &Pred,
2113                                           unsigned &PredReg,  in CanFormLdStDWord()  argument
2177   Pred = getInstrPredicate(*Op0, PredReg);  in CanFormLdStDWord()
2277         unsigned BaseReg = 0, PredReg = 0;  in RescheduleOps()  local
2285                                              Offset, PredReg, Pred, isT2)) {  in RescheduleOps()
2305             MIB.addImm(Offset).addImm(Pred).addReg(PredReg);  in RescheduleOps()
2319             MIB.addImm(Offset).addImm(Pred).addReg(PredReg);  in RescheduleOps()
2376       unsigned PredReg = 0;  in RescheduleLoadStoreInstrs()  local
2377       if (getInstrPredicate(MI, PredReg) != ARMCC::AL)  in RescheduleLoadStoreInstrs()