70   unsigned PredReg = 0;  in ReplaceTailWithBranchTo()  local
71   ARMCC::CondCodes CC = getInstrPredicate(*Tail, PredReg);  in ReplaceTailWithBranchTo()
118   unsigned PredReg = 0;  in isLegalToSplitMBBAt()  local
119   return getITInstrPredicate(*MBBI, PredReg) == ARMCC::AL;  in isLegalToSplitMBBAt()
236                                   ARMCC::CondCodes Pred, unsigned PredReg,  in emitT2RegPlusImmediate()  argument
242       .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);  in emitT2RegPlusImmediate()
259         .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);  in emitT2RegPlusImmediate()
266         .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);  in emitT2RegPlusImmediate()
275             .add(predOps(Pred, PredReg))  in emitT2RegPlusImmediate()
287             .add(predOps(Pred, PredReg))  in emitT2RegPlusImmediate()
487     unsigned PredReg;  in rewriteT2FrameIndex()  local
488     if (Offset == 0 && getInstrPredicate(MI, PredReg) == ARMCC::AL &&  in rewriteT2FrameIndex()
675                                            unsigned &PredReg) {  in getITInstrPredicate()  argument
679   return getInstrPredicate(MI, PredReg);  in getITInstrPredicate()