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Searched refs:FP_TO_SINT (Results 1 – 25 of 31) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp216 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, in getCastInstrCost()
249 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 }, in getCastInstrCost()
251 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 }, in getCastInstrCost()
253 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 }, in getCastInstrCost()
255 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 }, in getCastInstrCost()
257 { ISD::FP_TO_SINT, MVT::i16, MVT::f32, 2 }, in getCastInstrCost()
259 { ISD::FP_TO_SINT, MVT::i16, MVT::f64, 2 }, in getCastInstrCost()
261 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 2 }, in getCastInstrCost()
263 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 2 }, in getCastInstrCost()
265 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 10 }, in getCastInstrCost()
[all …]
H A DARMISelLowering.cpp167 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in addTypeForNEON()
172 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in addTypeForNEON()
718 setTargetDAGCombine(ISD::FP_TO_SINT); in ARMTargetLowering()
765 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in ARMTargetLowering()
767 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom); in ARMTargetLowering()
4838 if (Op.getOpcode() == ISD::FP_TO_SINT) in LowerFP_TO_INT()
7466 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X); in LowerSDIV_v4i8()
7505 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
8018 case ISD::FP_TO_SINT: in LowerOperation()
12128 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT; in PerformVCVTCombine()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp359 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 }, in getCastInstrCost()
360 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
361 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, in getCastInstrCost()
367 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2 }, in getCastInstrCost()
368 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 }, in getCastInstrCost()
369 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 1 }, in getCastInstrCost()
375 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, in getCastInstrCost()
376 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2 }, in getCastInstrCost()
381 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 }, in getCastInstrCost()
382 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, in getCastInstrCost()
[all …]
H A DAArch64ISelLowering.cpp234 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in AArch64TargetLowering()
235 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in AArch64TargetLowering()
236 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom); in AArch64TargetLowering()
560 setTargetDAGCombine(ISD::FP_TO_SINT); in AArch64TargetLowering()
649 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand); in AArch64TargetLowering()
807 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in addTypeForNEON()
2387 if (Op.getOpcode() == ISD::FP_TO_SINT) in LowerFP_TO_INT()
2942 case ISD::FP_TO_SINT: in LowerOperation()
9142 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT; in performFpToIntCombine()
11196 case ISD::FP_TO_SINT: in PerformDAGCombine()
[all …]
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h524 FP_TO_SINT, enumerator
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp381 case ISD::FP_TO_SINT: in LegalizeOp()
491 case ISD::FP_TO_SINT: in Promote()
568 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) in PromoteFP_TO_INT()
569 NewOpc = ISD::FP_TO_SINT; in PromoteFP_TO_INT()
H A DLegalizeFloatTypes.cpp764 case ISD::FP_TO_SINT: in SoftenFloatOperand()
930 bool Signed = N->getOpcode() == ISD::FP_TO_SINT; in SoftenFloatOp_FP_TO_XINT()
1563 case ISD::FP_TO_SINT: Res = ExpandFloatOp_FP_TO_SINT(N); break; in ExpandFloatOperand()
1769 case ISD::FP_TO_SINT: in PromoteFloatOperand()
H A DSelectionDAGDumper.cpp318 case ISD::FP_TO_SINT: return "fp_to_sint"; in getOperationName()
H A DLegalizeVectorTypes.cpp92 case ISD::FP_TO_SINT: in ScalarizeVectorResult()
540 case ISD::FP_TO_SINT: in ScalarizeVectorOperand()
778 case ISD::FP_TO_SINT: in SplitVectorResult()
1732 case ISD::FP_TO_SINT: in SplitVectorOperand()
2498 case ISD::FP_TO_SINT: in WidenVectorResult()
3708 case ISD::FP_TO_SINT: in WidenVectorOperand()
H A DLegalizeDAG.cpp2498 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { in PromoteLegalFP_TO_INT()
2499 OpToUse = ISD::FP_TO_SINT; in PromoteLegalFP_TO_INT()
2870 case ISD::FP_TO_SINT: in ExpandNode()
4159 case ISD::FP_TO_SINT: in PromoteNode()
4161 Node->getOpcode() == ISD::FP_TO_SINT, dl); in PromoteNode()
H A DTargetLowering.cpp4384 if (DstVT.isVector() && (!isOperationLegalOrCustom(ISD::FP_TO_SINT, DstVT) || in expandFP_TO_UINT()
4396 Result = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Src); in expandFP_TO_UINT()
4418 DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Val), Ofs); in expandFP_TO_UINT()
4425 SDValue True = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Src); in expandFP_TO_UINT()
4427 SDValue False = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, in expandFP_TO_UINT()
H A DLegalizeIntegerTypes.cpp116 case ISD::FP_TO_SINT: in PromoteIntegerResult()
477 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) in PromoteIntRes_FP_TO_XINT()
478 NewOpc = ISD::FP_TO_SINT; in PromoteIntRes_FP_TO_XINT()
1527 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; in ExpandIntegerResult()
H A DFastISel.cpp1878 return selectCast(I, ISD::FP_TO_SINT); in selectOperator()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1283 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, in getCastInstrCost()
1284 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, in getCastInstrCost()
1285 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, in getCastInstrCost()
1286 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, in getCastInstrCost()
1287 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, in getCastInstrCost()
1288 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, in getCastInstrCost()
1463 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 }, in getCastInstrCost()
1464 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 }, in getCastInstrCost()
1537 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 3 }, in getCastInstrCost()
H A DX86ISelLowering.cpp258 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); in X86TargetLowering()
271 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Expand); in X86TargetLowering()
734 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in X86TargetLowering()
1498 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal); in X86TargetLowering()
1589 setOperationAction(ISD::FP_TO_SINT, VT, Legal); in X86TargetLowering()
18432 bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT; in LowerFP_TO_INT()
24414 return DAG.getNode(ISD::FP_TO_SINT, dl, VT, Amt); in convertShiftLeftToScale()
26221 case ISD::FP_TO_SINT: in LowerOperation()
26627 case ISD::FP_TO_SINT: in ReplaceNodeResults()
26629 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT; in ReplaceNodeResults()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp368 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal); in PPCTargetLowering()
373 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
497 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
524 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
7014 Op.getOpcode() == ISD::FP_TO_SINT in LowerFP_TO_INTForReuse()
7078 Op.getOpcode() == ISD::FP_TO_SINT in LowerFP_TO_INTDirectMove()
7107 if (Op.getOpcode() == ISD::FP_TO_SINT) { in LowerFP_TO_INT()
7168 Op.getOpcode() == ISD::FP_TO_SINT) && in canReuseLoadAddress()
9733 case ISD::FP_TO_SINT: in ReplaceNodeResults()
12043 Opcode = ISD::FP_TO_SINT; in combineElementTruncationToVectorTruncation()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp163 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Custom); in R600TargetLowering()
164 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in R600TargetLowering()
276 setTargetDAGCombine(ISD::FP_TO_SINT); in R600TargetLowering()
666 case ISD::FP_TO_SINT: { in ReplaceNodeResults()
1864 case ISD::FP_TO_SINT: { in PerformDAGCombine()
H A DAMDGPUISelLowering.cpp382 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in AMDGPUTargetLowering()
404 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in AMDGPUTargetLowering()
1166 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); in LowerOperation()
1490 ISD::NodeType ToInt = Sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT; in LowerDIVREM24()
2528 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL, in LowerFP64_TO_INT()
/freebsd-12.1/contrib/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1509 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in SparcTargetLowering()
1511 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in SparcTargetLowering()
3017 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this, in LowerOperation()
3342 case ISD::FP_TO_SINT: in ReplaceNodeResults()
3348 libCall = ((N->getOpcode() == ISD::FP_TO_SINT) in ReplaceNodeResults()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp366 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in MipsTargetLowering()
377 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in MipsTargetLowering()
1232 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); in LowerOperation()
2586 if (Val.getOpcode() != ISD::FP_TO_SINT || in lowerFP_TO_SINT_STORE()
H A DMipsSEISelLowering.cpp350 setOperationAction(ISD::FP_TO_SINT, Ty, Legal); in addMSAIntType()
1893 return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1525 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote); in HexagonTargetLowering()
1526 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote); in HexagonTargetLowering()
1527 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote); in HexagonTargetLowering()
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1487 case FPToSI: return ISD::FP_TO_SINT; in InstructionOpcodeToISD()
/freebsd-12.1/contrib/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td453 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp370 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal); in SystemZTargetLowering()
371 setOperationAction(ISD::FP_TO_SINT, MVT::v2f64, Legal); in SystemZTargetLowering()

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