252   setOperationAction(ISD::FP_TO_SINT       , MVT::i1   , Promote);  in X86TargetLowering()
253   setOperationAction(ISD::FP_TO_SINT       , MVT::i8   , Promote);  in X86TargetLowering()
258     setOperationAction(ISD::FP_TO_SINT     , MVT::i64  , Custom);  in X86TargetLowering()
262       setOperationAction(ISD::FP_TO_SINT     , MVT::i16  , Promote);  in X86TargetLowering()
264       setOperationAction(ISD::FP_TO_SINT     , MVT::i32  , Custom);  in X86TargetLowering()
266       setOperationAction(ISD::FP_TO_SINT     , MVT::i16  , Custom);  in X86TargetLowering()
267       setOperationAction(ISD::FP_TO_SINT     , MVT::i32  , Custom);  in X86TargetLowering()
270     setOperationAction(ISD::FP_TO_SINT     , MVT::i16  , Promote);  in X86TargetLowering()
271     setOperationAction(ISD::FP_TO_SINT     , MVT::i32  , Expand);  in X86TargetLowering()
272     setOperationAction(ISD::FP_TO_SINT     , MVT::i64  , Expand);  in X86TargetLowering()
734     setOperationAction(ISD::FP_TO_SINT, VT, Expand);  in X86TargetLowering()
918     setOperationAction(ISD::FP_TO_SINT,         MVT::v4i32, Legal);  in X86TargetLowering()
919     setOperationAction(ISD::FP_TO_SINT,         MVT::v2i32, Custom);  in X86TargetLowering()
920     setOperationAction(ISD::FP_TO_SINT,         MVT::v2i16, Custom);  in X86TargetLowering()
923     setOperationAction(ISD::FP_TO_SINT,         MVT::v2i8,  Custom);  in X86TargetLowering()
924     setOperationAction(ISD::FP_TO_SINT,         MVT::v4i8,  Custom);  in X86TargetLowering()
925     setOperationAction(ISD::FP_TO_SINT,         MVT::v8i8,  Custom);  in X86TargetLowering()
926     setOperationAction(ISD::FP_TO_SINT,         MVT::v2i16, Custom);  in X86TargetLowering()
927     setOperationAction(ISD::FP_TO_SINT,         MVT::v4i16, Custom);  in X86TargetLowering()
940     setOperationAction(ISD::FP_TO_SINT,         MVT::v8i16, Custom);  in X86TargetLowering()
1126     setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v8i16, MVT::v8i32);  in X86TargetLowering()
1128     setOperationAction(ISD::FP_TO_SINT,         MVT::v8i32, Legal);  in X86TargetLowering()
1315     setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v8i1,  MVT::v8i32);  in X86TargetLowering()
1317     setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v4i1,  MVT::v4i32);  in X86TargetLowering()
1319     setOperationAction(ISD::FP_TO_SINT,         MVT::v2i1,  Custom);  in X86TargetLowering()
1399     setOperationAction(ISD::FP_TO_SINT,         MVT::v16i32, Legal);  in X86TargetLowering()
1400     setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v16i16, MVT::v16i32);  in X86TargetLowering()
1401     setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v16i8, MVT::v16i32);  in X86TargetLowering()
1402     setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v16i1, MVT::v16i32);  in X86TargetLowering()
1498       setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);  in X86TargetLowering()
1589         setOperationAction(ISD::FP_TO_SINT,     VT, Legal);  in X86TargetLowering()
1766       setOperationAction(ISD::FP_TO_SINT,    MVT::v2f32, Custom);  in X86TargetLowering()
18432   bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT;  in LowerFP_TO_INT()
24414     return DAG.getNode(ISD::FP_TO_SINT, dl, VT, Amt);  in convertShiftLeftToScale()
26221   case ISD::FP_TO_SINT:  in LowerOperation()
26627   case ISD::FP_TO_SINT:  in ReplaceNodeResults()
26629     bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;  in ReplaceNodeResults()
26642       SDValue Res = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v2i32, Src);  in ReplaceNodeResults()
26660       SDValue Res = DAG.getNode(ISD::FP_TO_SINT, dl, PromoteVT, Src);  in ReplaceNodeResults()
26715         Res = DAG.getNode(IsSigned ? ISD::FP_TO_SINT  in ReplaceNodeResults()
33240     if (SrcVT == MVT::v2i32 && N0.getOpcode() == ISD::FP_TO_SINT) {  in combineBitcast()