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Searched refs:EXTRACT_VECTOR_ELT (Results 1 – 25 of 35) sorted by relevance

12

/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp205 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Custom); in R600TargetLowering()
206 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Custom); in R600TargetLowering()
207 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); in R600TargetLowering()
208 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); in R600TargetLowering()
277 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); in R600TargetLowering()
478 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); in LowerOperation()
701 ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Vector, in vectorToVerticalVector()
719 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Op.getValueType(), in LowerEXTRACT_VECTOR_ELT()
1744 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in ReorganizeVector()
1753 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in ReorganizeVector()
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H A DSIISelLowering.cpp259 case ISD::EXTRACT_VECTOR_ELT: in SITargetLowering()
505 case ISD::EXTRACT_VECTOR_ELT: in SITargetLowering()
682 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); in SITargetLowering()
3650 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
3818 case ISD::EXTRACT_VECTOR_ELT: { in ReplaceNodeResults()
7819 case ISD::EXTRACT_VECTOR_ELT: in isCanonicalized()
8674 if (Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in performFMACombine()
8675 Op2.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in performFMACombine()
8692 if (FMAOp1.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in performFMACombine()
8693 FMAOp2.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in performFMACombine()
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H A DAMDGPUISelLowering.cpp1353 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); in split64BitValue()
1354 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); in split64BitValue()
1364 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); in getLoHalf64()
1372 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); in getHiHalf64()
2026 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One); in LowerFTRUNC()
2145 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, One); in LowerFROUND64()
2297 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); in LowerCTLZ_CTTZ()
2298 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); in LowerCTLZ_CTTZ()
2438 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, in LowerINT_TO_FP64()
2440 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, in LowerINT_TO_FP64()
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/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp266 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), in ScalarizeVecRes_EXTRACT_SUBVECTOR()
330 ISD::EXTRACT_VECTOR_ELT, DL, VT, Op, in ScalarizeVecRes_UnaryOp()
356 ISD::EXTRACT_VECTOR_ELT, DL, OpEltVT, Op, in ScalarizeVecRes_VecInregOp()
394 ISD::EXTRACT_VECTOR_ELT, DL, VT, Cond, in ScalarizeVecRes_VSELECT()
496 ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS, in ScalarizeVecRes_SETCC()
499 ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS, in ScalarizeVecRes_SETCC()
549 case ISD::EXTRACT_VECTOR_ELT: in ScalarizeVectorOperand()
2234 ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Op, in SplitVecOp_CONCAT_VECTORS()
2919 ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp, in WidenVecRes_Convert()
3855 ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp, in WidenVecOp_BITCAST()
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H A DLegalizeTypesGeneric.cpp130 ISD::EXTRACT_VECTOR_ELT, dl, ElemVT, CastInOp, in ExpandRes_BITCAST()
242 Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
246 Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
H A DLegalizeVectorOps.cpp1247 Oper = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, in ExpandStrictFPOp()
1278 ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS, in UnrollVSETCC()
1281 ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS, in UnrollVSETCC()
H A DLegalizeDAG.cpp996 case ISD::EXTRACT_VECTOR_ELT: in LegalizeOp()
2885 case ISD::EXTRACT_VECTOR_ELT: in ExpandNode()
2972 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0, in ExpandNode()
2976 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op1, in ExpandNode()
3719 ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(0), in ExpandNode()
3722 ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(1), in ExpandNode()
4107 Node->getOpcode() == ISD::EXTRACT_VECTOR_ELT || in PromoteNode()
4413 case ISD::EXTRACT_VECTOR_ELT: { in PromoteNode()
4448 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT, in PromoteNode()
4497 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT, in PromoteNode()
H A DLegalizeIntegerTypes.cpp69 case ISD::EXTRACT_VECTOR_ELT: in PromoteIntegerResult()
458 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, In, Op1); in PromoteIntRes_EXTRACT_VECTOR_ELT()
463 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, Op0, Op1); in PromoteIntRes_EXTRACT_VECTOR_ELT()
1053 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break; in PromoteIntegerOperand()
1512 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; in ExpandIntegerResult()
3654 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, in PromoteIntRes_EXTRACT_SUBVECTOR()
3752 ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Op, in PromoteIntRes_CONCAT_VECTORS()
3817 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, in PromoteIntOp_EXTRACT_VECTOR_ELT()
3854 ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Incoming, in PromoteIntOp_CONCAT_VECTORS()
H A DLegalizeFloatTypes.cpp74 case ISD::EXTRACT_VECTOR_ELT: in SoftenFloatResult()
179 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), in SoftenFloatRes_EXTRACT_VECTOR_ELT()
1066 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; in ExpandFloatResult()
1887 case ISD::EXTRACT_VECTOR_ELT: in PromoteFloatResult()
2029 SDValue NewVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IVT, in PromoteFloatRes_EXTRACT_VECTOR_ELT()
H A DSelectionDAG.cpp3023 case ISD::EXTRACT_VECTOR_ELT: { in computeKnownBits()
3658 case ISD::EXTRACT_VECTOR_ELT: { in ComputeNumSignBits()
3915 case ISD::EXTRACT_VECTOR_ELT: { in isKnownNeverNaN()
4000 if (Ops[i].getOpcode() != ISD::EXTRACT_VECTOR_ELT || in FoldBUILD_VECTOR()
4425 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && in getNode()
4965 case ISD::EXTRACT_VECTOR_ELT: in getNode()
4985 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, in getNode()
5031 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), in getNode()
8852 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT || in matchBinOpReduction()
8933 getNode(ISD::EXTRACT_VECTOR_ELT, dl, OperandEltVT, Operand, in UnrollVectorOp()
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H A DSelectionDAGDumper.cpp273 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt"; in getOperationName()
H A DDAGCombiner.cpp4618 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitAND()
9716 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitTRUNCATE()
9735 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, TrTy, in visitTRUNCATE()
9894 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, VT, in visitTRUNCATE()
14249 (Val.getOpcode() == ISD::EXTRACT_VECTOR_ELT || in MergeStoresOfConstantsOrVecElts()
14418 if (Val.getOpcode() != ISD::EXTRACT_VECTOR_ELT && in getStoreMergeCandidates()
15511 if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitINSERT_VECTOR_ELT()
15844 return Use->getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitEXTRACT_VECTOR_ELT()
16320 if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in reduceBuildVecToShuffle()
16569 if ((Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT) && in visitBUILD_VECTOR()
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/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h339 EXTRACT_VECTOR_ELT, enumerator
/freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp232 setOperationAction(ISD::EXTRACT_VECTOR_ELT, T, Custom); in WebAssemblyTargetLowering()
237 setOperationAction(ISD::EXTRACT_VECTOR_ELT, T, Custom); in WebAssemblyTargetLowering()
897 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
1115 if (Op.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT) in LowerSIGN_EXTEND_INREG()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp101 setOperationAction(ISD::EXTRACT_VECTOR_ELT, T, Custom); in initializeHVXLowering()
192 setOperationAction(ISD::EXTRACT_VECTOR_ELT, BoolV, Custom); in initializeHVXLowering()
418 if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in buildHvxVectorReg()
1068 if (V.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in LowerHvxConcatVectors()
1070 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NTy, in LowerHvxConcatVectors()
1558 case ISD::EXTRACT_VECTOR_ELT: return LowerHvxExtractElement(Op, DAG); in LowerHvxOperation()
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp327 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal); in SystemZTargetLowering()
528 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); in SystemZTargetLowering()
4355 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in tryBuildVectorShuffle()
4700 SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntVT, in lowerEXTRACT_VECTOR_ELT()
4880 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
5214 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Op, in combineExtract()
5227 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineTruncateExtract()
5493 Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineFP_ROUND()
5501 U->getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineFP_ROUND()
5540 Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineFP_EXTEND()
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H A DSystemZISelDAGToDAG.cpp700 if (Index.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in selectBDVAddr12Only()
1171 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in tryScatter()
/freebsd-12.1/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp389 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom); in NVPTXTargetLowering()
1895 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp, in LowerCONCAT_VECTORS()
1943 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vector, in LowerEXTRACT_VECTOR_ELT()
1945 SDValue E1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vector, in LowerEXTRACT_VECTOR_ELT()
2087 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
2273 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f16, Val, in LowerSTOREVector()
2275 SDValue E1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f16, Val, in LowerSTOREVector()
2283 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val, in LowerSTOREVector()
2498 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, LoadVT, P, in LowerFormalArguments()
4620 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, SubVector, in ReplaceLoadVector()
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/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp395 if (ISD == ISD::EXTRACT_VECTOR_ELT || in getVectorInstrCost()
H A DPPCISelLowering.cpp615 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand); in PPCTargetLowering()
701 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal); in PPCTargetLowering()
897 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f64, Legal); in PPCTargetLowering()
946 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f32, Legal); in PPCTargetLowering()
987 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4i1, Custom); in PPCTargetLowering()
9142 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Op, in LowerBSWAP()
9400 ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, Value, in LowerVectorStore()
12214 if (Extract.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in combineBVOfVecSExt()
12327 if(Ext1.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in DAGCombineBuildVector()
12328 Ext2.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in DAGCombineBuildVector()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp1856 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); in X86TargetLowering()
6604 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in getFauxShuffleMask()
7706 if (Opc != ISD::EXTRACT_VECTOR_ELT) { in buildFromShuffleMostly()
8816 if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTORAsVariablePermute()
18528 if (LHS.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in lowerAddSubToHorizontalOp()
18529 RHS.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in lowerAddSubToHorizontalOp()
18782 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerVectorAllZeroTest()
24278 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, in GetSplatValue()
33759 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in combineExtractVectorElt()
39607 if (V.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineFMA()
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/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp163 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
2547 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, in LowerReturn()
4962 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res, in LowerFCOPYSIGN()
6460 if (Value->getOpcode() == ISD::EXTRACT_VECTOR_ELT && in LowerBUILD_VECTOR()
6615 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) { in ReconstructShuffle()
7090 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, in LowerVECTOR_SHUFFLE()
9887 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in AddCombineBUILD_VECTORToVPADDL()
9897 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT in AddCombineBUILD_VECTORToVPADDL()
12015 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, in PerformSTORECombine()
12054 StVal.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in PerformSTORECombine()
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/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp323 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom); in addMSAIntType()
376 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal); in addMSAFloatType()
462 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG); in LowerOperation()
1745 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), in lowerINTRINSIC_WO_CHAIN()
1763 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), in lowerINTRINSIC_WO_CHAIN()
/freebsd-12.1/contrib/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp244 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
247 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
861 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, in LowerCall_32()
864 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, in LowerCall_32()
1456 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Legal); in SparcTargetLowering()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp778 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
2802 SDValue ExtractTrunc = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerTruncateVectorStore()
2910 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
5956 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in ReconstructShuffle()
7254 if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
7357 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in LowerBUILD_VECTOR()
7524 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!"); in LowerEXTRACT_VECTOR_ELT()
7554 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec, in LowerEXTRACT_VECTOR_ELT()
9550 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in tryCombineFixedPointConvert()
9574 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane); in tryCombineFixedPointConvert()
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