Lines Matching refs:EXTRACT_VECTOR_ELT

615       setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);  in PPCTargetLowering()
701       setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);  in PPCTargetLowering()
704         setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);  in PPCTargetLowering()
711         setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Legal);  in PPCTargetLowering()
712         setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Legal);  in PPCTargetLowering()
713         setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);  in PPCTargetLowering()
714         setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);  in PPCTargetLowering()
716       setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);  in PPCTargetLowering()
897     setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f64, Legal);  in PPCTargetLowering()
946     setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f32, Legal);  in PPCTargetLowering()
987     setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4i1, Custom);  in PPCTargetLowering()
9142   Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Op,  in LowerBSWAP()
9400           ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, Value,  in LowerVectorStore()
9660   case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);  in LowerOperation()
12214     if (Extract.getOpcode() != ISD::EXTRACT_VECTOR_ELT)  in combineBVOfVecSExt()
12327   if(Ext1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||  in DAGCombineBuildVector()
12328      Ext2.getOpcode() != ISD::EXTRACT_VECTOR_ELT)  in DAGCombineBuildVector()
14582         ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Bitcast,  in combineTRUNCATE()