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Searched refs:BaseReg (Results 1 – 25 of 61) sorted by relevance

123

/freebsd-12.1/contrib/llvm/lib/Target/ARC/
H A DARCRegisterInfo.cpp47 unsigned BaseReg = FrameReg; in ReplaceFrameIndex() local
52 .addReg(BaseReg) in ReplaceFrameIndex()
61 BaseReg = RS->FindUnusedReg(&ARC::GPR32RegClass); in ReplaceFrameIndex()
62 if (!BaseReg) { in ReplaceFrameIndex()
67 BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj); in ReplaceFrameIndex()
68 assert(BaseReg && "Register scavenging failed."); in ReplaceFrameIndex()
69 LLVM_DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI) in ReplaceFrameIndex()
73 RS->setRegUsed(BaseReg); in ReplaceFrameIndex()
77 .addReg(BaseReg, RegState::Define) in ReplaceFrameIndex()
93 .addReg(BaseReg, KillState) in ReplaceFrameIndex()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIFixupVectorISel.cpp87 unsigned &BaseReg, in findSRegBaseAndIndex() argument
117 BaseReg = DefInst->getOperand(2).getReg(); in findSRegBaseAndIndex()
134 MI = MRI.getUniqueVRegDef(BaseReg); in findSRegBaseAndIndex()
138 BaseReg = MI->getOperand(1).getReg(); in findSRegBaseAndIndex()
139 BaseRC = MRI.getRegClass(BaseReg); in findSRegBaseAndIndex()
143 if (!TRI->isSGPRReg(MRI, BaseReg)) in findSRegBaseAndIndex()
149 MRI.clearKillFlags(BaseReg); in findSRegBaseAndIndex()
177 unsigned BaseReg = 0; in fixupGlobalSaddr() local
180 if (!findSRegBaseAndIndex(Op, BaseReg, IndexReg, MRI, TRI)) in fixupGlobalSaddr()
194 NewGlob->addOperand(MF, MachineOperand::CreateReg(BaseReg, false)); in fixupGlobalSaddr()
H A DSIRegisterInfo.h93 unsigned BaseReg, int FrameIdx,
96 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
99 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DThumbRegisterInfo.cpp132 (BaseReg != 0 && !isARMLowRegister(BaseReg)); in emitThumbRegPlusImmInReg()
144 assert(BaseReg == ARM::SP && "Unexpected!"); in emitThumbRegPlusImmInReg()
176 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); in emitThumbRegPlusImmInReg()
220 if (BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
232 if (BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
238 } else if (DestReg == BaseReg) { in emitThumbRegPlusImmediate()
241 } else if (isARMLowRegister(BaseReg)) { in emitThumbRegPlusImmediate()
255 if (DestReg == BaseReg) { in emitThumbRegPlusImmediate()
315 MIB.addReg(BaseReg, RegState::Kill); in emitThumbRegPlusImmediate()
321 BaseReg = DestReg; in emitThumbRegPlusImmediate()
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H A DThumb2InstrInfo.cpp239 if (NumBytes == 0 && DestReg != BaseReg) { in emitT2RegPlusImmediate()
241 .addReg(BaseReg, RegState::Kill) in emitT2RegPlusImmediate()
251 if (DestReg != ARM::SP && DestReg != BaseReg && in emitT2RegPlusImmediate()
273 .addReg(BaseReg) in emitT2RegPlusImmediate()
285 .addReg(BaseReg) in emitT2RegPlusImmediate()
298 if (DestReg == ARM::SP && BaseReg != ARM::SP) { in emitT2RegPlusImmediate()
301 .addReg(BaseReg) in emitT2RegPlusImmediate()
304 BaseReg = ARM::SP; in emitT2RegPlusImmediate()
309 if (BaseReg == ARM::SP) { in emitT2RegPlusImmediate()
315 .addReg(BaseReg) in emitT2RegPlusImmediate()
[all …]
H A DARMBaseRegisterInfo.h167 unsigned BaseReg, int FrameIdx,
169 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
171 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
H A DARMBaseRegisterInfo.cpp613 unsigned BaseReg, int FrameIdx, in materializeFrameBaseRegister() argument
628 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
630 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg) in materializeFrameBaseRegister()
637 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex() argument
656 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); in resolveFrameIndex()
659 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII); in resolveFrameIndex()
665 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, in isFrameOffsetLegal() argument
706 NumBits = (BaseReg == ARM::SP ? 8 : 5); in isFrameOffsetLegal()
H A DARMLoadStoreOptimizer.cpp1636 unsigned BaseReg = BaseOp.getReg(); in FixInvalidRegPairOp() local
1644 bool Errata602117 = EvenReg == BaseReg && in FixInvalidRegPairOp()
1677 .addReg(BaseReg, getKillRegState(BaseKill)) in FixInvalidRegPairOp()
1684 .addReg(BaseReg, getKillRegState(BaseKill)) in FixInvalidRegPairOp()
1704 if (isLd && TRI->regsOverlap(EvenReg, BaseReg)) { in FixInvalidRegPairOp()
1705 assert(!TRI->regsOverlap(OddReg, BaseReg)); in FixInvalidRegPairOp()
1719 if (EvenReg == BaseReg) in FixInvalidRegPairOp()
2176 BaseReg = Op0->getOperand(1).getReg(); in CanFormLdStDWord()
2277 unsigned BaseReg = 0, PredReg = 0; in RescheduleOps() local
2299 .addReg(BaseReg); in RescheduleOps()
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/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DLocalStackSlotAllocation.cpp269 lookupCandidateBaseReg(unsigned BaseReg, in lookupCandidateBaseReg() argument
278 return TRI->isFrameOffsetLegal(&MI, BaseReg, Offset); in lookupCandidateBaseReg()
343 unsigned BaseReg = 0; in insertFrameReferenceRegisters() local
387 lookupCandidateBaseReg(BaseReg, BaseOffset, FrameSizeAdjust, in insertFrameReferenceRegisters()
389 LLVM_DEBUG(dbgs() << " Reusing base register " << BaseReg << "\n"); in insertFrameReferenceRegisters()
406 BaseReg, BaseOffset, FrameSizeAdjust, in insertFrameReferenceRegisters()
415 BaseReg = Fn.getRegInfo().createVirtualRegister(RC); in insertFrameReferenceRegisters()
417 LLVM_DEBUG(dbgs() << " Materializing base register " << BaseReg in insertFrameReferenceRegisters()
424 TRI->materializeFrameBaseRegister(Entry, BaseReg, FrameIdx, in insertFrameReferenceRegisters()
435 assert(BaseReg != 0 && "Unable to allocate virtual base register!"); in insertFrameReferenceRegisters()
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/freebsd-12.1/contrib/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp985 if (BaseReg != 0 && in CheckBaseRegAndIndexRegAndScale()
986 !(BaseReg == X86::RIP || BaseReg == X86::EIP || in CheckBaseRegAndIndexRegAndScale()
1006 if (((BaseReg == X86::RIP || BaseReg == X86::EIP) && IndexReg != 0) || in CheckBaseRegAndIndexRegAndScale()
1016 (Is64BitMode || (BaseReg != X86::BX && BaseReg != X86::BP && in CheckBaseRegAndIndexRegAndScale()
1017 BaseReg != X86::SI && BaseReg != X86::DI))) { in CheckBaseRegAndIndexRegAndScale()
1049 if ((BaseReg != X86::BX && BaseReg != X86::BP) || in CheckBaseRegAndIndexRegAndScale()
1059 (BaseReg == X86::RIP || BaseReg == X86::EIP)) { in CheckBaseRegAndIndexRegAndScale()
1384 BaseReg = BaseReg ? BaseReg : 1; in CreateMemForInlineAsm()
1896 if (Scale == 0 && BaseReg != X86::ESP && BaseReg != X86::RSP && in ParseIntelOperand()
1922 if ((BaseReg == X86::SI || BaseReg == X86::DI) && in ParseIntelOperand()
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H A DX86Operand.h61 unsigned BaseReg; member
134 if (Mem.BaseReg) in print()
135 OS << ",BaseReg=" << X86IntelInstPrinter::getRegisterName(Mem.BaseReg); in print()
184 return Mem.BaseReg; in getMemBaseReg()
573 Res->Mem.BaseReg = 0;
588 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
593 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
601 Res->Mem.BaseReg = BaseReg;
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64LoadStoreOptimizer.cpp1075 BaseReg == getLdStBaseOp(MI).getReg() && in findMatchingStore()
1090 if (!ModifiedRegUnits.available(BaseReg)) in findMatchingStore()
1301 if (!ModifiedRegUnits.available(BaseReg)) in findMatchingInsn()
1397 if (MI.getOperand(0).getReg() != BaseReg || in isMatchingUpdateInsn()
1398 MI.getOperand(1).getReg() != BaseReg) in isMatchingUpdateInsn()
1453 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg)) in findMatchingUpdateInsnForward()
1479 if (!ModifiedRegUnits.available(BaseReg) || in findMatchingUpdateInsnForward()
1480 !UsedRegUnits.available(BaseReg)) in findMatchingUpdateInsnForward()
1505 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg)) in findMatchingUpdateInsnBackward()
1532 if (!ModifiedRegUnits.available(BaseReg) || in findMatchingUpdateInsnBackward()
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H A DAArch64RegisterInfo.h100 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
102 void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg,
105 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
H A DAArch64FalkorHWPFFix.cpp217 unsigned BaseReg = 0; member
646 unsigned BaseReg = MI.getOperand(BaseRegIdx).getReg(); in getLoadInfo() local
647 if (BaseReg == AArch64::SP || BaseReg == AArch64::WSP) in getLoadInfo()
652 LI.BaseReg = BaseReg; in getLoadInfo()
662 unsigned Base = TRI->getEncodingValue(LI.BaseReg); in getTag()
756 NewLdI.BaseReg = ScratchReg; in runOnLoop()
773 .addReg(LdI.BaseReg) in runOnLoop()
786 TII->get(AArch64::ORRXrs), LdI.BaseReg) in runOnLoop()
H A DAArch64StorePairSuppress.cpp155 unsigned BaseReg = BaseOp->getReg(); in runOnMachineFunction() local
156 if (PrevBaseReg == BaseReg) { in runOnMachineFunction()
165 PrevBaseReg = BaseReg; in runOnMachineFunction()
H A DAArch64RegisterInfo.cpp391 unsigned BaseReg, in isFrameOffsetLegal() argument
402 unsigned BaseReg, in materializeFrameBaseRegister() argument
414 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
417 BuildMI(*MBB, Ins, DL, MCID, BaseReg) in materializeFrameBaseRegister()
423 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex() argument
435 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII); in resolveFrameIndex()
/freebsd-12.1/contrib/llvm/lib/Target/X86/InstPrinter/
H A DX86ATTInstPrinter.cpp113 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); in printMemReference() local
124 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) in printMemReference()
131 if (IndexReg.getReg() || BaseReg.getReg()) { in printMemReference()
133 if (BaseReg.getReg()) in printMemReference()
H A DX86IntelInstPrinter.cpp74 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printMemReference() local
85 if (BaseReg.getReg()) { in printMemReference()
104 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { in printMemReference()
/freebsd-12.1/contrib/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp72 if (is16BitMode(STI) && BaseReg.getReg() == 0 && in Is16BitMemOperand()
75 if ((BaseReg.getReg() != 0 && in Is16BitMemOperand()
213 if ((BaseReg.getReg() != 0 && in Is32BitMemOperand()
218 if (BaseReg.getReg() == X86::EIP) { in Is32BitMemOperand()
234 if ((BaseReg.getReg() != 0 && in Is64BitMemOperand()
387 unsigned BaseReg = Base.getReg(); in emitMemModRMByte() local
391 if (BaseReg == X86::RIP || in emitMemModRMByte()
446 if (BaseReg) { in emitMemModRMByte()
516 (!is64BitMode(STI) || BaseReg != 0)) { in emitMemModRMByte()
569 if (BaseReg == 0) { in emitMemModRMByte()
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/freebsd-12.1/contrib/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp271 emitRRI(Opcode, SrcReg, BaseReg, Offset, IDLoc, STI); in emitStoreWithImmOffset()
293 if (BaseReg != Mips::ZERO) in emitStoreWithImmOffset()
294 emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI); in emitStoreWithImmOffset()
310 if (BaseReg != Mips::ZERO) in emitStoreWithSymOffset()
311 emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI); in emitStoreWithSymOffset()
325 emitRRI(Opcode, DstReg, BaseReg, Offset, IDLoc, STI); in emitLoadWithImmOffset()
346 if (BaseReg != Mips::ZERO) in emitLoadWithImmOffset()
347 emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI); in emitLoadWithImmOffset()
358 unsigned BaseReg, in emitLoadWithSymOffset() argument
370 if (BaseReg != Mips::ZERO) in emitLoadWithSymOffset()
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/freebsd-12.1/contrib/llvm/lib/Target/Lanai/AsmParser/
H A DLanaiAsmParser.cpp129 unsigned BaseReg; member
171 return Mem.BaseReg; in getMemBaseReg()
613 Op->Mem.BaseReg = 0; in MorphToMemImm()
621 MorphToMemRegReg(unsigned BaseReg, std::unique_ptr<LanaiOperand> Op, in MorphToMemRegReg()
625 Op->Mem.BaseReg = BaseReg; in MorphToMemRegReg()
633 MorphToMemRegImm(unsigned BaseReg, std::unique_ptr<LanaiOperand> Op, in MorphToMemRegImm()
637 Op->Mem.BaseReg = BaseReg; in MorphToMemRegImm()
884 unsigned BaseReg = 0; in parseMemoryOperand() local
941 BaseReg = Op->getReg(); in parseMemoryOperand()
969 if (!BaseReg || Lexer.isNot(AsmToken::RBrac)) { in parseMemoryOperand()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86InsertPrefetch.cpp83 unsigned BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg(); in IsMemOpCompatibleWithPrefetch() local
85 return (BaseReg == 0 || in IsMemOpCompatibleWithPrefetch()
86 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) || in IsMemOpCompatibleWithPrefetch()
87 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg)) && in IsMemOpCompatibleWithPrefetch()
H A DX86AsmPrinter.cpp263 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printLeaMemReference() local
268 bool HasBaseReg = BaseReg.getReg() != 0; in printLeaMemReference()
270 BaseReg.getReg() == X86::RIP) in printLeaMemReference()
328 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printIntelMemReference() local
343 if (BaseReg.getReg()) { in printIntelMemReference()
361 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { in printIntelMemReference()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.h129 unsigned BaseReg, int FrameIdx,
131 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
133 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
/freebsd-12.1/contrib/llvm/include/llvm/MC/MCParser/
H A DMCTargetAsmParser.h65 StringRef BaseReg; member
70 BaseReg(StringRef()), IndexReg(StringRef()), in NeedBracs()
89 BaseReg = baseReg; in IntelExpr()
92 return BaseReg.size(); in hasBaseReg()

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