Lines Matching refs:BaseReg
1608 bool RegDeadKill, bool RegUndef, unsigned BaseReg, in InsertLDR_STR() argument
1615 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef)); in InsertLDR_STR()
1621 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef)); in InsertLDR_STR()
1636 unsigned BaseReg = BaseOp.getReg(); in FixInvalidRegPairOp() local
1644 bool Errata602117 = EvenReg == BaseReg && in FixInvalidRegPairOp()
1677 .addReg(BaseReg, getKillRegState(BaseKill)) in FixInvalidRegPairOp()
1684 .addReg(BaseReg, getKillRegState(BaseKill)) in FixInvalidRegPairOp()
1704 if (isLd && TRI->regsOverlap(EvenReg, BaseReg)) { in FixInvalidRegPairOp()
1705 assert(!TRI->regsOverlap(OddReg, BaseReg)); in FixInvalidRegPairOp()
1707 false, BaseReg, false, BaseUndef, Pred, PredReg, TII); in FixInvalidRegPairOp()
1709 false, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII); in FixInvalidRegPairOp()
1719 if (EvenReg == BaseReg) in FixInvalidRegPairOp()
1722 EvenUndef, BaseReg, false, BaseUndef, Pred, PredReg, TII); in FixInvalidRegPairOp()
1724 OddUndef, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII); in FixInvalidRegPairOp()
2033 unsigned &OddReg, unsigned &BaseReg,
2112 unsigned &BaseReg, int &Offset, in CanFormLdStDWord() argument
2176 BaseReg = Op0->getOperand(1).getReg(); in CanFormLdStDWord()
2277 unsigned BaseReg = 0, PredReg = 0; in RescheduleOps() local
2284 FirstReg, SecondReg, BaseReg, in RescheduleOps()
2299 .addReg(BaseReg); in RescheduleOps()
2313 .addReg(BaseReg); in RescheduleOps()