337     unsigned BaseReg, IndexReg, TmpReg, Scale;  member in __anon3be435310111::X86AsmParser::IntelExprStateMachine
348         : State(IES_INIT), PrevState(IES_ERROR), BaseReg(0), IndexReg(0),  in IntelExprStateMachine()
355     unsigned getBaseReg() { return BaseReg; }  in getBaseReg()
456           if (!BaseReg) {  in onPlus()
457             BaseReg = TmpReg;  in onPlus()
509           if (!BaseReg) {  in onMinus()
510             BaseReg = TmpReg;  in onMinus()
741           if (!BaseReg) {  in onRBrac()
742             BaseReg = TmpReg;  in onRBrac()
845   CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg,
978 static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg,  in CheckBaseRegAndIndexRegAndScale()  argument
985   if (BaseReg != 0 &&  in CheckBaseRegAndIndexRegAndScale()
986       !(BaseReg == X86::RIP || BaseReg == X86::EIP ||  in CheckBaseRegAndIndexRegAndScale()
987         X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) ||  in CheckBaseRegAndIndexRegAndScale()
988         X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) ||  in CheckBaseRegAndIndexRegAndScale()
989         X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg))) {  in CheckBaseRegAndIndexRegAndScale()
1006   if (((BaseReg == X86::RIP || BaseReg == X86::EIP) && IndexReg != 0) ||  in CheckBaseRegAndIndexRegAndScale()
1015   if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&  in CheckBaseRegAndIndexRegAndScale()
1016       (Is64BitMode || (BaseReg != X86::BX && BaseReg != X86::BP &&  in CheckBaseRegAndIndexRegAndScale()
1017                        BaseReg != X86::SI && BaseReg != X86::DI))) {  in CheckBaseRegAndIndexRegAndScale()
1022   if (BaseReg == 0 &&  in CheckBaseRegAndIndexRegAndScale()
1028   if (BaseReg != 0 && IndexReg != 0) {  in CheckBaseRegAndIndexRegAndScale()
1029     if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&  in CheckBaseRegAndIndexRegAndScale()
1036     if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) &&  in CheckBaseRegAndIndexRegAndScale()
1043     if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg)) {  in CheckBaseRegAndIndexRegAndScale()
1049       if ((BaseReg != X86::BX && BaseReg != X86::BP) ||  in CheckBaseRegAndIndexRegAndScale()
1058   if (!Is64BitMode && BaseReg != 0 &&  in CheckBaseRegAndIndexRegAndScale()
1059       (BaseReg == X86::RIP || BaseReg == X86::EIP)) {  in CheckBaseRegAndIndexRegAndScale()
1284         unsigned OrigReg = OrigOp.Mem.BaseReg;  in VerifyAndAdjustOperands()
1285         unsigned FinalReg = FinalOp.Mem.BaseReg;  in VerifyAndAdjustOperands()
1319         FinalOp.Mem.BaseReg = FinalReg;  in VerifyAndAdjustOperands()
1347     unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg,  in CreateMemForInlineAsm()  argument
1378   if (IsGlobalLV && (BaseReg || IndexReg)) {  in CreateMemForInlineAsm()
1384     BaseReg = BaseReg ? BaseReg : 1;  in CreateMemForInlineAsm()
1385     return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg,  in CreateMemForInlineAsm()
1892   unsigned BaseReg = SM.getBaseReg();  in ParseIntelOperand()  local
1896   if (Scale == 0 && BaseReg != X86::ESP && BaseReg != X86::RSP &&  in ParseIntelOperand()
1898     std::swap(BaseReg, IndexReg);  in ParseIntelOperand()
1906       (X86MCRegisterClasses[X86::VR128XRegClassID].contains(BaseReg) ||  in ParseIntelOperand()
1907        X86MCRegisterClasses[X86::VR256XRegClassID].contains(BaseReg) ||  in ParseIntelOperand()
1908        X86MCRegisterClasses[X86::VR512RegClassID].contains(BaseReg)))  in ParseIntelOperand()
1909     std::swap(BaseReg, IndexReg);  in ParseIntelOperand()
1922   if ((BaseReg == X86::SI || BaseReg == X86::DI) &&  in ParseIntelOperand()
1924     std::swap(BaseReg, IndexReg);  in ParseIntelOperand()
1926   if ((BaseReg || IndexReg) &&  in ParseIntelOperand()
1927       CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),  in ParseIntelOperand()
1931     return CreateMemForInlineAsm(RegNo, Disp, BaseReg, IndexReg,  in ParseIntelOperand()
1934   if (!(BaseReg || IndexReg || RegNo))  in ParseIntelOperand()
1937                                BaseReg, IndexReg, Scale, Start, End, Size);  in ParseIntelOperand()
2193   unsigned BaseReg = 0, IndexReg = 0, Scale = 1;  in ParseMemOperand()  local
2205     BaseReg = cast<X86MCExpr>(E)->getRegNo();  in ParseMemOperand()
2206     if (BaseReg == X86::EIZ || BaseReg == X86::RIZ)  in ParseMemOperand()
2235         if (BaseReg == X86::RIP)  in ParseMemOperand()
2253             if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&  in ParseMemOperand()
2272   if (BaseReg == X86::DX && IndexReg == 0 && Scale == 1 && SegReg == 0 &&  in ParseMemOperand()
2276   if (CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),  in ParseMemOperand()
2280   if (SegReg || BaseReg || IndexReg)  in ParseMemOperand()
2281     return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg,  in ParseMemOperand()