| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCCodeEmitter.cpp | 267 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue() local 546 unsigned ShiftVal = AArch64_AM::getShiftValue(ShiftOpnd); in getImm8OptLsl() local 573 unsigned ShiftVal = AArch64_AM::getShiftValue(MO.getImm()); in getMoveVecShifterOpValue() local
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| H A D | AArch64InstPrinter.cpp | 1081 unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val); in printArithExtend() local
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVMatInt.cpp | 390 for (unsigned ShiftVal = 0; ShiftVal < Size; ShiftVal += PlatRegSize) { in getIntMatCost() local
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 1234 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2(); in emitAddSub() local 1256 uint64_t ShiftVal = C->getZExtValue(); in emitAddSub() local 1603 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2(); in emitLogicalOp() local 1618 uint64_t ShiftVal = C->getZExtValue(); in emitLogicalOp() local 4589 uint64_t ShiftVal = C->getValue().logBase2(); in selectMul() local 4652 uint64_t ShiftVal = C->getZExtValue(); in selectShift() local
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| H A D | AArch64ISelDAGToDAG.cpp | 562 unsigned ShiftVal = CSD->getZExtValue(); in isWorthFoldingSHL() local 848 unsigned ShiftVal = 0; in SelectArithExtendedRegister() local 901 unsigned ShiftVal = 0; in SelectArithUXTXRegister() local 1130 unsigned ShiftVal = CSD->getZExtValue(); in SelectExtendedSHL() local
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| H A D | AArch64InstrInfo.cpp | 885 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local 912 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local 920 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local
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| H A D | AArch64TargetTransformInfo.cpp | 163 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { in getIntImmCost() local
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMParallelDSP.cpp | 789 Value *ShiftVal = ConstantInt::get(LoadTy, OffsetTy->getBitWidth()); in CreateWideLoad() local
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| /llvm-project-15.0.7/bolt/lib/Target/AArch64/ |
| H A D | AArch64MCPlusBuilder.cpp | 547 unsigned ShiftVal = AArch64_AM::getArithShiftValue(OperandExtension); in analyzeIndirectBranchFragment() local
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1523 auto matchFirstShift = [&](const MachineInstr *MI, uint64_t &ShiftVal) { in matchShiftOfShiftedLogic() 1600 unsigned &ShiftVal) { in matchCombineMulToShl() 1612 unsigned &ShiftVal) { in applyCombineMulToShl() 1898 unsigned &ShiftVal) { in matchCombineShiftToUnmerge() 1922 const unsigned &ShiftVal) { in applyCombineShiftToUnmerge()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 2161 uint32_t ShiftVal = Shift->getZExtValue(); in SelectS_BFE() local 2182 uint32_t ShiftVal = Shift->getZExtValue(); in SelectS_BFE() local
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| H A D | AMDGPUISelLowering.cpp | 4110 SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32); in PerformDAGCombine() local
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InstCombineIntrinsic.cpp | 388 APInt ShiftVal = COp->getValue(); in simplifyX86varShift() local
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| H A D | X86TargetTransformInfo.cpp | 4872 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { in getIntImmCost() local
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| H A D | X86ISelLowering.cpp | 8518 uint64_t ShiftVal = N.getConstantOperandVal(1); in getFauxShuffleMask() local 9071 SDValue ShiftVal = DAG.getTargetConstant(NumBits / 8, dl, MVT::i8); in getVShift() local 19821 int ShiftVal = (IdxVal % 4) * 8; in LowerEXTRACT_VECTOR_ELT() local 19832 int ShiftVal = (IdxVal % 2) * 8; in LowerEXTRACT_VECTOR_ELT() local 37127 const APInt &ShiftVal = Op.getConstantOperandAPInt(1); in ComputeNumSignBitsForTargetNode() local 37138 APInt ShiftVal = Op.getConstantOperandAPInt(1); in ComputeNumSignBitsForTargetNode() local 47109 unsigned ShiftVal = N->getConstantOperandVal(1); in combineVectorShiftImm() local 47672 unsigned ShiftVal = SplatVal.countTrailingOnes(); in combineAndMaskToShift() local
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 1984 uint64_t ShiftVal = C->getZExtValue(); in selectShift() local
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| /llvm-project-15.0.7/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 13745 unsigned ShiftVal = cast<llvm::ConstantInt>(Ops[2])->getZExtValue() & 0xff; in EmitX86BuiltinExpr() local 13787 unsigned ShiftVal = cast<llvm::ConstantInt>(Ops[2])->getZExtValue() & 0xff; in EmitX86BuiltinExpr() local 13873 unsigned ShiftVal = cast<llvm::ConstantInt>(Ops[1])->getZExtValue() & 0xff; in EmitX86BuiltinExpr() local 13903 unsigned ShiftVal = cast<llvm::ConstantInt>(Ops[1])->getZExtValue() & 0xff; in EmitX86BuiltinExpr() local 13934 unsigned ShiftVal = cast<llvm::ConstantInt>(Ops[1])->getZExtValue() & 0xff; in EmitX86BuiltinExpr() local 13956 unsigned ShiftVal = cast<llvm::ConstantInt>(Ops[1])->getZExtValue() & 0xff; in EmitX86BuiltinExpr() local
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 2390 auto ShiftVal = DAG.getSplatValue(Op.getOperand(1)); in LowerShift() local
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| /llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCasts.cpp | 508 ConstantInt *ShiftVal = nullptr; in foldVecTruncToExtElt() local
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| H A D | InstCombineCompares.cpp | 2123 const APInt *ShiftVal; in foldICmpShlConstant() local
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 6551 unsigned ShiftVal = AArch64_AM::getShifterImm(ShType, Val); in selectShiftedRegister() local 6642 uint64_t ShiftVal = 0; in selectArithExtendedRegister() local
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| /llvm-project-15.0.7/llvm/lib/IR/ |
| H A D | AutoUpgrade.cpp | 1228 unsigned ShiftVal = cast<llvm::ConstantInt>(Shift)->getZExtValue(); in UpgradeX86ALIGNIntrinsics() local
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 2508 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) { in isSimpleShift() 2666 unsigned NewCCMask, ShiftVal; in adjustForTestUnderMask() local
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 5064 unsigned ShiftVal = 0; in Select() local
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| /llvm-project-15.0.7/llvm/lib/Analysis/ |
| H A D | ValueTracking.cpp | 2604 auto ShiftVal = Shift->getLimitedValue(BitWidth - 1); in isKnownNonZero() local
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