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Searched defs:ExtVal (Results 1 – 12 of 12) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp679 int64_t ExtVal = IsBool ? CI->getZExtValue() : CI->getSExtValue(); in lowerAsmOperandForConstraint() local
H A DLegalizerHelper.cpp3139 auto ExtVal = MIRBuilder.buildAnyExtOrTrunc(NewSrcTy, SrcReg); in lowerStore() local
/llvm-project-15.0.7/llvm/unittests/Support/
H A DTargetParserTest.cpp1486 uint64_t ExtVal = 0; in TEST() local
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2424 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val, in LowerSTOREVector() local
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp2214 ZExtInst *ExtVal = dyn_cast<ZExtInst>(CI->getArgOperand(0)); in optimizeCallInst() local
4318 Value *ExtVal = SExt; in promoteOperandForTruncAndAnyExt() local
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetLowering.h2886 virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; } in isVectorLoadExtDesirable()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp1977 SDValue ExtVal = SDValue(CurDAG->getMachineNode(PPC::INSERT_SUBREG, dl, in ExtendToInt64() local
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp5180 int64_t ExtVal = in LowerAsmOperandForConstraint() local
H A DDAGCombiner.cpp13210 SDValue ExtVal = N0.getOperand(1); in visitTRUNCATE() local
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp5733 SDValue ExtVal = DAG.getNode(ISD::BITCAST, SL, IntVT, in lowerINSERT_VECTOR_ELT() local
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp14885 uint64_t ExtVal = C->getZExtValue(); in performSVEAndCombine() local
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp55865 int64_t ExtVal = ExtOpc == ISD::ZERO_EXTEND ? CST->getZExtValue() in LowerAsmOperandForConstraint() local