Move TableGen's parser and entry point into a library

This is the first step towards splitting LLVM and Clang's tblgen executables.

llvm-svn: 140951

Switch to ArrayRef<CodeGenRegisterClass*>.

This makes it possible to allocate CodeGenRegisterClass instances
dynamically and reorder them.

llvm-svn: 140816

Unconstify Inits

Remove const qualifiers from Init references, per Chris' request.

llvm-svn: 136531

[AVX] Constify Inits

Make references to Inits const everywhere. This is the final step
before making them unique.

llvm-svn: 136485

Revert r134921, 134917, 134908 and 134907. They're causing failures
in multiple buildbots.

llvm-svn: 134936

[AVX] Make Inits Foldable

Manage Inits in a FoldingSet. This provides several benefits:

- Memory for Inits is properly managed

- Duplicate Inits are folded into Flyweights, saving memory

- It en

[AVX] Make Inits Foldable

Manage Inits in a FoldingSet. This provides several benefits:

- Memory for Inits is properly managed

- Duplicate Inits are folded into Flyweights, saving memory

- It enforces const-correctness, protecting against certain classes
of bugs

The above benefits allow Inits to be used in more contexts, which in
turn provides more dynamism to TableGen. This enhanced capability
will be used by the AVX code generator to a fold common patterns
together.

llvm-svn: 134907

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Add support for alternative register names, useful for instructions whose operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton tha

Add support for alternative register names, useful for instructions whose operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0.
Patch by Jim Grosbach.

llvm-svn: 133940

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Store CodeGenRegisters as pointers so they won't be reallocated.

Reuse the CodeGenRegBank DenseMap in a few places that would build their
own or use linear search.

llvm-svn: 133333

Fix formatting.

llvm-svn: 133164

Add a new MVT::untyped. This will be used in future work for modelling ISA features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-o

Add a new MVT::untyped. This will be used in future work for modelling ISA features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match.

llvm-svn: 133106

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Give CodeGenRegisterClass a real sorted member set.

Make the Elements vector private and expose an ArrayRef through
getOrder() instead. getOrder will eventually provide multiple
user-specified alloc

Give CodeGenRegisterClass a real sorted member set.

Make the Elements vector private and expose an ArrayRef through
getOrder() instead. getOrder will eventually provide multiple
user-specified allocation orders.

Use the sorted member set for member and subclass tests. Clean up a lot
of ad hoc searches.

llvm-svn: 133040

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Move the list of register classes into CodeGenRegBank as well.

No functional change intended.

llvm-svn: 133029

Move the list of registers into CodeGenRegBank.

Also move the sub-register index computations from RegisterInfoEmitter
into CodeGenRegBank.

llvm-svn: 132865

Move some sub-register index calculations to CodeGenRegisters.cpp

Create a new CodeGenRegBank class that will eventually hold all the code
that computes the register structure from Records.

llvm-sv

Move some sub-register index calculations to CodeGenRegisters.cpp

Create a new CodeGenRegBank class that will eventually hold all the code
that computes the register structure from Records.

llvm-svn: 132849

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Move TableGen's register bank classes to their own source file.

I'll be moving some more code there to gather all of the
register-specific stuff in one place. Currently it is shared between
CodeGenT

Move TableGen's register bank classes to their own source file.

I'll be moving some more code there to gather all of the
register-specific stuff in one place. Currently it is shared between
CodeGenTarget and RegisterInfoEmitter.

The plan is that CodeGenRegisters can compute the full register bank
structure while RegisterInfoEmitter only will handle the printing part.

llvm-svn: 132788

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Make it possible to have unallocatable register classes.

Some register classes are only used for instruction operand constraints.
They should never be used for virtual registers. Previously, those
r

Make it possible to have unallocatable register classes.

Some register classes are only used for instruction operand constraints.
They should never be used for virtual registers. Previously, those
register classes were given an empty allocation order, but now you can
say 'let isAllocatable=0' in the register class definition.

TableGen calculates if a register is part of any allocatable register
class, and makes that information available in TargetRegisterDesc::inAllocatableClass.

The goal here is to eliminate use cases for overriding allocation_order_*
methods.

llvm-svn: 132508

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Change how tblgen generates attributes for intrinsics to use a single
switch. With this newfound organization, teach tblgen how not to give
all intrinsics the 'nounwind' attribute. Introduce a new

Change how tblgen generates attributes for intrinsics to use a single
switch. With this newfound organization, teach tblgen how not to give
all intrinsics the 'nounwind' attribute. Introduce a new intrinsic,
llvm.eh.resume, which does not have this attribute. Documentation and uses
to follow.

llvm-svn: 132252

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Teach TableGen to automatically generate missing SubRegIndex instances.

The RegisterInfo.td file should only specify the indexes that sources need to
refer to. The rest is inferred.

llvm-svn: 131058

Don't allow per-register spill size and alignment.

These values were not used for anything. Spill size and alignment is a property
of the register class, not the register.

llvm-svn: 129906

Prefer cheap registers for busy live ranges.

On the x86-64 and thumb2 targets, some registers are more expensive to encode
than others in the same register class.

Add a CostPerUse field to the Tabl

Prefer cheap registers for busy live ranges.

On the x86-64 and thumb2 targets, some registers are more expensive to encode
than others in the same register class.

Add a CostPerUse field to the TableGen register description, and make it
available from TRI->getCostPerUse. This represents the cost of a REX prefix or a
32-bit instruction encoding required by choosing a high register.

Teach the greedy register allocator to prefer cheap registers for busy live
ranges (as indicated by spill weight).

llvm-svn: 129864

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Make the register enum value part of the CodeGenRegister struct.

llvm-svn: 127448

Trailing whitespace.

llvm-svn: 127447

Flag -> Glue, the ongoing saga

llvm-svn: 122513

rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for
something that just glues two nodes together, even if it is
sometimes used for flags.

llvm-svn: 122310

various cleanups to tblgen, patch by Garrison Venn!

llvm-svn: 121837