1 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This class wraps target description classes used by the various code 11 // generation TableGen backends. This makes it easier to access the data and 12 // provides a single place that needs to check it for validity. All of these 13 // classes throw exceptions on error conditions. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "CodeGenTarget.h" 18 #include "CodeGenIntrinsics.h" 19 #include "Record.h" 20 #include "llvm/ADT/StringExtras.h" 21 #include "llvm/ADT/STLExtras.h" 22 #include "llvm/Support/CommandLine.h" 23 #include <algorithm> 24 using namespace llvm; 25 26 static cl::opt<unsigned> 27 AsmParserNum("asmparsernum", cl::init(0), 28 cl::desc("Make -gen-asm-parser emit assembly parser #N")); 29 30 static cl::opt<unsigned> 31 AsmWriterNum("asmwriternum", cl::init(0), 32 cl::desc("Make -gen-asm-writer emit assembly writer #N")); 33 34 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen 35 /// record corresponds to. 36 MVT::SimpleValueType llvm::getValueType(Record *Rec) { 37 return (MVT::SimpleValueType)Rec->getValueAsInt("Value"); 38 } 39 40 std::string llvm::getName(MVT::SimpleValueType T) { 41 switch (T) { 42 case MVT::Other: return "UNKNOWN"; 43 case MVT::iPTR: return "TLI.getPointerTy()"; 44 case MVT::iPTRAny: return "TLI.getPointerTy()"; 45 default: return getEnumName(T); 46 } 47 } 48 49 std::string llvm::getEnumName(MVT::SimpleValueType T) { 50 switch (T) { 51 case MVT::Other: return "MVT::Other"; 52 case MVT::i1: return "MVT::i1"; 53 case MVT::i8: return "MVT::i8"; 54 case MVT::i16: return "MVT::i16"; 55 case MVT::i32: return "MVT::i32"; 56 case MVT::i64: return "MVT::i64"; 57 case MVT::i128: return "MVT::i128"; 58 case MVT::iAny: return "MVT::iAny"; 59 case MVT::fAny: return "MVT::fAny"; 60 case MVT::vAny: return "MVT::vAny"; 61 case MVT::f32: return "MVT::f32"; 62 case MVT::f64: return "MVT::f64"; 63 case MVT::f80: return "MVT::f80"; 64 case MVT::f128: return "MVT::f128"; 65 case MVT::ppcf128: return "MVT::ppcf128"; 66 case MVT::x86mmx: return "MVT::x86mmx"; 67 case MVT::Glue: return "MVT::Glue"; 68 case MVT::isVoid: return "MVT::isVoid"; 69 case MVT::v2i8: return "MVT::v2i8"; 70 case MVT::v4i8: return "MVT::v4i8"; 71 case MVT::v8i8: return "MVT::v8i8"; 72 case MVT::v16i8: return "MVT::v16i8"; 73 case MVT::v32i8: return "MVT::v32i8"; 74 case MVT::v2i16: return "MVT::v2i16"; 75 case MVT::v4i16: return "MVT::v4i16"; 76 case MVT::v8i16: return "MVT::v8i16"; 77 case MVT::v16i16: return "MVT::v16i16"; 78 case MVT::v2i32: return "MVT::v2i32"; 79 case MVT::v4i32: return "MVT::v4i32"; 80 case MVT::v8i32: return "MVT::v8i32"; 81 case MVT::v1i64: return "MVT::v1i64"; 82 case MVT::v2i64: return "MVT::v2i64"; 83 case MVT::v4i64: return "MVT::v4i64"; 84 case MVT::v8i64: return "MVT::v8i64"; 85 case MVT::v2f32: return "MVT::v2f32"; 86 case MVT::v4f32: return "MVT::v4f32"; 87 case MVT::v8f32: return "MVT::v8f32"; 88 case MVT::v2f64: return "MVT::v2f64"; 89 case MVT::v4f64: return "MVT::v4f64"; 90 case MVT::Metadata: return "MVT::Metadata"; 91 case MVT::iPTR: return "MVT::iPTR"; 92 case MVT::iPTRAny: return "MVT::iPTRAny"; 93 default: assert(0 && "ILLEGAL VALUE TYPE!"); return ""; 94 } 95 } 96 97 /// getQualifiedName - Return the name of the specified record, with a 98 /// namespace qualifier if the record contains one. 99 /// 100 std::string llvm::getQualifiedName(const Record *R) { 101 std::string Namespace = R->getValueAsString("Namespace"); 102 if (Namespace.empty()) return R->getName(); 103 return Namespace + "::" + R->getName(); 104 } 105 106 107 108 109 /// getTarget - Return the current instance of the Target class. 110 /// 111 CodeGenTarget::CodeGenTarget(RecordKeeper &records) : Records(records) { 112 std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target"); 113 if (Targets.size() == 0) 114 throw std::string("ERROR: No 'Target' subclasses defined!"); 115 if (Targets.size() != 1) 116 throw std::string("ERROR: Multiple subclasses of Target defined!"); 117 TargetRec = Targets[0]; 118 } 119 120 121 const std::string &CodeGenTarget::getName() const { 122 return TargetRec->getName(); 123 } 124 125 std::string CodeGenTarget::getInstNamespace() const { 126 for (inst_iterator i = inst_begin(), e = inst_end(); i != e; ++i) { 127 // Make sure not to pick up "TargetOpcode" by accidentally getting 128 // the namespace off the PHI instruction or something. 129 if ((*i)->Namespace != "TargetOpcode") 130 return (*i)->Namespace; 131 } 132 133 return ""; 134 } 135 136 Record *CodeGenTarget::getInstructionSet() const { 137 return TargetRec->getValueAsDef("InstructionSet"); 138 } 139 140 141 /// getAsmParser - Return the AssemblyParser definition for this target. 142 /// 143 Record *CodeGenTarget::getAsmParser() const { 144 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers"); 145 if (AsmParserNum >= LI.size()) 146 throw "Target does not have an AsmParser #" + utostr(AsmParserNum) + "!"; 147 return LI[AsmParserNum]; 148 } 149 150 /// getAsmWriter - Return the AssemblyWriter definition for this target. 151 /// 152 Record *CodeGenTarget::getAsmWriter() const { 153 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters"); 154 if (AsmWriterNum >= LI.size()) 155 throw "Target does not have an AsmWriter #" + utostr(AsmWriterNum) + "!"; 156 return LI[AsmWriterNum]; 157 } 158 159 void CodeGenTarget::ReadRegisters() const { 160 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); 161 if (Regs.empty()) 162 throw std::string("No 'Register' subclasses defined!"); 163 std::sort(Regs.begin(), Regs.end(), LessRecord()); 164 165 Registers.reserve(Regs.size()); 166 Registers.assign(Regs.begin(), Regs.end()); 167 // Assign the enumeration values. 168 for (unsigned i = 0, e = Registers.size(); i != e; ++i) 169 Registers[i].EnumValue = i + 1; 170 } 171 172 CodeGenRegister::CodeGenRegister(Record *R) : TheDef(R) { 173 DeclaredSpillSize = R->getValueAsInt("SpillSize"); 174 DeclaredSpillAlignment = R->getValueAsInt("SpillAlignment"); 175 CostPerUse = R->getValueAsInt("CostPerUse"); 176 } 177 178 const std::string &CodeGenRegister::getName() const { 179 return TheDef->getName(); 180 } 181 182 void CodeGenTarget::ReadSubRegIndices() const { 183 SubRegIndices = Records.getAllDerivedDefinitions("SubRegIndex"); 184 std::sort(SubRegIndices.begin(), SubRegIndices.end(), LessRecord()); 185 } 186 187 void CodeGenTarget::ReadRegisterClasses() const { 188 std::vector<Record*> RegClasses = 189 Records.getAllDerivedDefinitions("RegisterClass"); 190 if (RegClasses.empty()) 191 throw std::string("No 'RegisterClass' subclasses defined!"); 192 193 RegisterClasses.reserve(RegClasses.size()); 194 RegisterClasses.assign(RegClasses.begin(), RegClasses.end()); 195 } 196 197 /// getRegisterByName - If there is a register with the specific AsmName, 198 /// return it. 199 const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const { 200 const std::vector<CodeGenRegister> &Regs = getRegisters(); 201 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 202 const CodeGenRegister &Reg = Regs[i]; 203 if (Reg.TheDef->getValueAsString("AsmName") == Name) 204 return &Reg; 205 } 206 207 return 0; 208 } 209 210 std::vector<MVT::SimpleValueType> CodeGenTarget:: 211 getRegisterVTs(Record *R) const { 212 std::vector<MVT::SimpleValueType> Result; 213 const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses(); 214 for (unsigned i = 0, e = RCs.size(); i != e; ++i) { 215 const CodeGenRegisterClass &RC = RegisterClasses[i]; 216 for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) { 217 if (R == RC.Elements[ei]) { 218 const std::vector<MVT::SimpleValueType> &InVTs = RC.getValueTypes(); 219 Result.insert(Result.end(), InVTs.begin(), InVTs.end()); 220 } 221 } 222 } 223 224 // Remove duplicates. 225 array_pod_sort(Result.begin(), Result.end()); 226 Result.erase(std::unique(Result.begin(), Result.end()), Result.end()); 227 return Result; 228 } 229 230 231 CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) { 232 // Rename anonymous register classes. 233 if (R->getName().size() > 9 && R->getName()[9] == '.') { 234 static unsigned AnonCounter = 0; 235 R->setName("AnonRegClass_"+utostr(AnonCounter++)); 236 } 237 238 std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes"); 239 for (unsigned i = 0, e = TypeList.size(); i != e; ++i) { 240 Record *Type = TypeList[i]; 241 if (!Type->isSubClassOf("ValueType")) 242 throw "RegTypes list member '" + Type->getName() + 243 "' does not derive from the ValueType class!"; 244 VTs.push_back(getValueType(Type)); 245 } 246 assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!"); 247 248 std::vector<Record*> RegList = R->getValueAsListOfDefs("MemberList"); 249 for (unsigned i = 0, e = RegList.size(); i != e; ++i) { 250 Record *Reg = RegList[i]; 251 if (!Reg->isSubClassOf("Register")) 252 throw "Register Class member '" + Reg->getName() + 253 "' does not derive from the Register class!"; 254 Elements.push_back(Reg); 255 } 256 257 // SubRegClasses is a list<dag> containing (RC, subregindex, ...) dags. 258 ListInit *SRC = R->getValueAsListInit("SubRegClasses"); 259 for (ListInit::const_iterator i = SRC->begin(), e = SRC->end(); i != e; ++i) { 260 DagInit *DAG = dynamic_cast<DagInit*>(*i); 261 if (!DAG) throw "SubRegClasses must contain DAGs"; 262 DefInit *DAGOp = dynamic_cast<DefInit*>(DAG->getOperator()); 263 Record *RCRec; 264 if (!DAGOp || !(RCRec = DAGOp->getDef())->isSubClassOf("RegisterClass")) 265 throw "Operator '" + DAG->getOperator()->getAsString() + 266 "' in SubRegClasses is not a RegisterClass"; 267 // Iterate over args, all SubRegIndex instances. 268 for (DagInit::const_arg_iterator ai = DAG->arg_begin(), ae = DAG->arg_end(); 269 ai != ae; ++ai) { 270 DefInit *Idx = dynamic_cast<DefInit*>(*ai); 271 Record *IdxRec; 272 if (!Idx || !(IdxRec = Idx->getDef())->isSubClassOf("SubRegIndex")) 273 throw "Argument '" + (*ai)->getAsString() + 274 "' in SubRegClasses is not a SubRegIndex"; 275 if (!SubRegClasses.insert(std::make_pair(IdxRec, RCRec)).second) 276 throw "SubRegIndex '" + IdxRec->getName() + "' mentioned twice"; 277 } 278 } 279 280 // Allow targets to override the size in bits of the RegisterClass. 281 unsigned Size = R->getValueAsInt("Size"); 282 283 Namespace = R->getValueAsString("Namespace"); 284 SpillSize = Size ? Size : EVT(VTs[0]).getSizeInBits(); 285 SpillAlignment = R->getValueAsInt("Alignment"); 286 CopyCost = R->getValueAsInt("CopyCost"); 287 MethodBodies = R->getValueAsCode("MethodBodies"); 288 MethodProtos = R->getValueAsCode("MethodProtos"); 289 } 290 291 const std::string &CodeGenRegisterClass::getName() const { 292 return TheDef->getName(); 293 } 294 295 void CodeGenTarget::ReadLegalValueTypes() const { 296 const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses(); 297 for (unsigned i = 0, e = RCs.size(); i != e; ++i) 298 for (unsigned ri = 0, re = RCs[i].VTs.size(); ri != re; ++ri) 299 LegalValueTypes.push_back(RCs[i].VTs[ri]); 300 301 // Remove duplicates. 302 std::sort(LegalValueTypes.begin(), LegalValueTypes.end()); 303 LegalValueTypes.erase(std::unique(LegalValueTypes.begin(), 304 LegalValueTypes.end()), 305 LegalValueTypes.end()); 306 } 307 308 309 void CodeGenTarget::ReadInstructions() const { 310 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction"); 311 if (Insts.size() <= 2) 312 throw std::string("No 'Instruction' subclasses defined!"); 313 314 // Parse the instructions defined in the .td file. 315 for (unsigned i = 0, e = Insts.size(); i != e; ++i) 316 Instructions[Insts[i]] = new CodeGenInstruction(Insts[i]); 317 } 318 319 static const CodeGenInstruction * 320 GetInstByName(const char *Name, 321 const DenseMap<const Record*, CodeGenInstruction*> &Insts, 322 RecordKeeper &Records) { 323 const Record *Rec = Records.getDef(Name); 324 325 DenseMap<const Record*, CodeGenInstruction*>::const_iterator 326 I = Insts.find(Rec); 327 if (Rec == 0 || I == Insts.end()) 328 throw std::string("Could not find '") + Name + "' instruction!"; 329 return I->second; 330 } 331 332 namespace { 333 /// SortInstByName - Sorting predicate to sort instructions by name. 334 /// 335 struct SortInstByName { 336 bool operator()(const CodeGenInstruction *Rec1, 337 const CodeGenInstruction *Rec2) const { 338 return Rec1->TheDef->getName() < Rec2->TheDef->getName(); 339 } 340 }; 341 } 342 343 /// getInstructionsByEnumValue - Return all of the instructions defined by the 344 /// target, ordered by their enum value. 345 void CodeGenTarget::ComputeInstrsByEnum() const { 346 // The ordering here must match the ordering in TargetOpcodes.h. 347 const char *const FixedInstrs[] = { 348 "PHI", 349 "INLINEASM", 350 "PROLOG_LABEL", 351 "EH_LABEL", 352 "GC_LABEL", 353 "KILL", 354 "EXTRACT_SUBREG", 355 "INSERT_SUBREG", 356 "IMPLICIT_DEF", 357 "SUBREG_TO_REG", 358 "COPY_TO_REGCLASS", 359 "DBG_VALUE", 360 "REG_SEQUENCE", 361 "COPY", 362 0 363 }; 364 const DenseMap<const Record*, CodeGenInstruction*> &Insts = getInstructions(); 365 for (const char *const *p = FixedInstrs; *p; ++p) { 366 const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records); 367 assert(Instr && "Missing target independent instruction"); 368 assert(Instr->Namespace == "TargetOpcode" && "Bad namespace"); 369 InstrsByEnum.push_back(Instr); 370 } 371 unsigned EndOfPredefines = InstrsByEnum.size(); 372 373 for (DenseMap<const Record*, CodeGenInstruction*>::const_iterator 374 I = Insts.begin(), E = Insts.end(); I != E; ++I) { 375 const CodeGenInstruction *CGI = I->second; 376 if (CGI->Namespace != "TargetOpcode") 377 InstrsByEnum.push_back(CGI); 378 } 379 380 assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr"); 381 382 // All of the instructions are now in random order based on the map iteration. 383 // Sort them by name. 384 std::sort(InstrsByEnum.begin()+EndOfPredefines, InstrsByEnum.end(), 385 SortInstByName()); 386 } 387 388 389 /// isLittleEndianEncoding - Return whether this target encodes its instruction 390 /// in little-endian format, i.e. bits laid out in the order [0..n] 391 /// 392 bool CodeGenTarget::isLittleEndianEncoding() const { 393 return getInstructionSet()->getValueAsBit("isLittleEndianEncoding"); 394 } 395 396 //===----------------------------------------------------------------------===// 397 // ComplexPattern implementation 398 // 399 ComplexPattern::ComplexPattern(Record *R) { 400 Ty = ::getValueType(R->getValueAsDef("Ty")); 401 NumOperands = R->getValueAsInt("NumOperands"); 402 SelectFunc = R->getValueAsString("SelectFunc"); 403 RootNodes = R->getValueAsListOfDefs("RootNodes"); 404 405 // Parse the properties. 406 Properties = 0; 407 std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties"); 408 for (unsigned i = 0, e = PropList.size(); i != e; ++i) 409 if (PropList[i]->getName() == "SDNPHasChain") { 410 Properties |= 1 << SDNPHasChain; 411 } else if (PropList[i]->getName() == "SDNPOptInGlue") { 412 Properties |= 1 << SDNPOptInGlue; 413 } else if (PropList[i]->getName() == "SDNPMayStore") { 414 Properties |= 1 << SDNPMayStore; 415 } else if (PropList[i]->getName() == "SDNPMayLoad") { 416 Properties |= 1 << SDNPMayLoad; 417 } else if (PropList[i]->getName() == "SDNPSideEffect") { 418 Properties |= 1 << SDNPSideEffect; 419 } else if (PropList[i]->getName() == "SDNPMemOperand") { 420 Properties |= 1 << SDNPMemOperand; 421 } else if (PropList[i]->getName() == "SDNPVariadic") { 422 Properties |= 1 << SDNPVariadic; 423 } else if (PropList[i]->getName() == "SDNPWantRoot") { 424 Properties |= 1 << SDNPWantRoot; 425 } else if (PropList[i]->getName() == "SDNPWantParent") { 426 Properties |= 1 << SDNPWantParent; 427 } else { 428 errs() << "Unsupported SD Node property '" << PropList[i]->getName() 429 << "' on ComplexPattern '" << R->getName() << "'!\n"; 430 exit(1); 431 } 432 } 433 434 //===----------------------------------------------------------------------===// 435 // CodeGenIntrinsic Implementation 436 //===----------------------------------------------------------------------===// 437 438 std::vector<CodeGenIntrinsic> llvm::LoadIntrinsics(const RecordKeeper &RC, 439 bool TargetOnly) { 440 std::vector<Record*> I = RC.getAllDerivedDefinitions("Intrinsic"); 441 442 std::vector<CodeGenIntrinsic> Result; 443 444 for (unsigned i = 0, e = I.size(); i != e; ++i) { 445 bool isTarget = I[i]->getValueAsBit("isTarget"); 446 if (isTarget == TargetOnly) 447 Result.push_back(CodeGenIntrinsic(I[i])); 448 } 449 return Result; 450 } 451 452 CodeGenIntrinsic::CodeGenIntrinsic(Record *R) { 453 TheDef = R; 454 std::string DefName = R->getName(); 455 ModRef = ReadWriteMem; 456 isOverloaded = false; 457 isCommutative = false; 458 459 if (DefName.size() <= 4 || 460 std::string(DefName.begin(), DefName.begin() + 4) != "int_") 461 throw "Intrinsic '" + DefName + "' does not start with 'int_'!"; 462 463 EnumName = std::string(DefName.begin()+4, DefName.end()); 464 465 if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field. 466 GCCBuiltinName = R->getValueAsString("GCCBuiltinName"); 467 468 TargetPrefix = R->getValueAsString("TargetPrefix"); 469 Name = R->getValueAsString("LLVMName"); 470 471 if (Name == "") { 472 // If an explicit name isn't specified, derive one from the DefName. 473 Name = "llvm."; 474 475 for (unsigned i = 0, e = EnumName.size(); i != e; ++i) 476 Name += (EnumName[i] == '_') ? '.' : EnumName[i]; 477 } else { 478 // Verify it starts with "llvm.". 479 if (Name.size() <= 5 || 480 std::string(Name.begin(), Name.begin() + 5) != "llvm.") 481 throw "Intrinsic '" + DefName + "'s name does not start with 'llvm.'!"; 482 } 483 484 // If TargetPrefix is specified, make sure that Name starts with 485 // "llvm.<targetprefix>.". 486 if (!TargetPrefix.empty()) { 487 if (Name.size() < 6+TargetPrefix.size() || 488 std::string(Name.begin() + 5, Name.begin() + 6 + TargetPrefix.size()) 489 != (TargetPrefix + ".")) 490 throw "Intrinsic '" + DefName + "' does not start with 'llvm." + 491 TargetPrefix + ".'!"; 492 } 493 494 // Parse the list of return types. 495 std::vector<MVT::SimpleValueType> OverloadedVTs; 496 ListInit *TypeList = R->getValueAsListInit("RetTypes"); 497 for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) { 498 Record *TyEl = TypeList->getElementAsRecord(i); 499 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 500 MVT::SimpleValueType VT; 501 if (TyEl->isSubClassOf("LLVMMatchType")) { 502 unsigned MatchTy = TyEl->getValueAsInt("Number"); 503 assert(MatchTy < OverloadedVTs.size() && 504 "Invalid matching number!"); 505 VT = OverloadedVTs[MatchTy]; 506 // It only makes sense to use the extended and truncated vector element 507 // variants with iAny types; otherwise, if the intrinsic is not 508 // overloaded, all the types can be specified directly. 509 assert(((!TyEl->isSubClassOf("LLVMExtendedElementVectorType") && 510 !TyEl->isSubClassOf("LLVMTruncatedElementVectorType")) || 511 VT == MVT::iAny || VT == MVT::vAny) && 512 "Expected iAny or vAny type"); 513 } else { 514 VT = getValueType(TyEl->getValueAsDef("VT")); 515 } 516 if (EVT(VT).isOverloaded()) { 517 OverloadedVTs.push_back(VT); 518 isOverloaded = true; 519 } 520 521 // Reject invalid types. 522 if (VT == MVT::isVoid) 523 throw "Intrinsic '" + DefName + " has void in result type list!"; 524 525 IS.RetVTs.push_back(VT); 526 IS.RetTypeDefs.push_back(TyEl); 527 } 528 529 // Parse the list of parameter types. 530 TypeList = R->getValueAsListInit("ParamTypes"); 531 for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) { 532 Record *TyEl = TypeList->getElementAsRecord(i); 533 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 534 MVT::SimpleValueType VT; 535 if (TyEl->isSubClassOf("LLVMMatchType")) { 536 unsigned MatchTy = TyEl->getValueAsInt("Number"); 537 assert(MatchTy < OverloadedVTs.size() && 538 "Invalid matching number!"); 539 VT = OverloadedVTs[MatchTy]; 540 // It only makes sense to use the extended and truncated vector element 541 // variants with iAny types; otherwise, if the intrinsic is not 542 // overloaded, all the types can be specified directly. 543 assert(((!TyEl->isSubClassOf("LLVMExtendedElementVectorType") && 544 !TyEl->isSubClassOf("LLVMTruncatedElementVectorType")) || 545 VT == MVT::iAny || VT == MVT::vAny) && 546 "Expected iAny or vAny type"); 547 } else 548 VT = getValueType(TyEl->getValueAsDef("VT")); 549 550 if (EVT(VT).isOverloaded()) { 551 OverloadedVTs.push_back(VT); 552 isOverloaded = true; 553 } 554 555 // Reject invalid types. 556 if (VT == MVT::isVoid && i != e-1 /*void at end means varargs*/) 557 throw "Intrinsic '" + DefName + " has void in result type list!"; 558 559 IS.ParamVTs.push_back(VT); 560 IS.ParamTypeDefs.push_back(TyEl); 561 } 562 563 // Parse the intrinsic properties. 564 ListInit *PropList = R->getValueAsListInit("Properties"); 565 for (unsigned i = 0, e = PropList->getSize(); i != e; ++i) { 566 Record *Property = PropList->getElementAsRecord(i); 567 assert(Property->isSubClassOf("IntrinsicProperty") && 568 "Expected a property!"); 569 570 if (Property->getName() == "IntrNoMem") 571 ModRef = NoMem; 572 else if (Property->getName() == "IntrReadArgMem") 573 ModRef = ReadArgMem; 574 else if (Property->getName() == "IntrReadMem") 575 ModRef = ReadMem; 576 else if (Property->getName() == "IntrReadWriteArgMem") 577 ModRef = ReadWriteArgMem; 578 else if (Property->getName() == "Commutative") 579 isCommutative = true; 580 else if (Property->isSubClassOf("NoCapture")) { 581 unsigned ArgNo = Property->getValueAsInt("ArgNo"); 582 ArgumentAttributes.push_back(std::make_pair(ArgNo, NoCapture)); 583 } else 584 assert(0 && "Unknown property!"); 585 } 586 } 587