[BOLT][TEST] Update fptr.testThe test exercises an implicit ptr-to-int conversion which is made an error inD129881. We acknowledge the error but still want to test this case.Add `-Wno-int-convers
[BOLT][TEST] Update fptr.testThe test exercises an implicit ptr-to-int conversion which is made an error inD129881. We acknowledge the error but still want to test this case.Add `-Wno-int-conversion` to silence the error.Reviewed By: maksfbDifferential Revision: https://reviews.llvm.org/D130546
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[BOLT] Fix instrumentation problem with floating pointIf BOLT instrumentation runtime uses XMM registers, it can interferewith the user program causing crashes and unexpected behavior. Thishappen
[BOLT] Fix instrumentation problem with floating pointIf BOLT instrumentation runtime uses XMM registers, it can interferewith the user program causing crashes and unexpected behavior. Thishappens as the instrumentation code preserves general purpose registersonly.Build BOLT instrumentation runtime with "-mno-sse".Reviewed By: AmirDifferential Revision: https://reviews.llvm.org/D128960
[BOLT] Fix EH trampoline backout codeWhen SplitFunctions pass adds a trampoline code for exception landingpads (limited to shared objects), it may increase the size of the hotfragment making it l
[BOLT] Fix EH trampoline backout codeWhen SplitFunctions pass adds a trampoline code for exception landingpads (limited to shared objects), it may increase the size of the hotfragment making it larger than the whole function pre-split. When thishappens, the pass reverts the splitting action by restoring the originalblock order and marking all blocks hot.However, if createEHTrampolines() added new blocks to the CFG andmodified invoke instructions, simply restoring the original block layoutwill not suffice as the new CFG has more blocks.For proper backout of the split, modify the original layout by mergingin trampoline blocks immediately before their matching targets. As aresult, the number of blocks increases, but the number of instructionsand the function size remains the same as pre-split.Add an assertion for the number of blocks when updating a functionlayout.Reviewed By: rafaulerDifferential Revision: https://reviews.llvm.org/D128696
[BOLT] Mark option values of --split-functions deprecatedThe SplitFunctions pass does not distinguish between various splittingmodes anymore. This change updates the command line interface torefl
[BOLT] Mark option values of --split-functions deprecatedThe SplitFunctions pass does not distinguish between various splittingmodes anymore. This change updates the command line interface toreflect this behavior by deprecating values passed to the--split-function option.Reviewed By: rafaulerDifferential Revision: https://reviews.llvm.org/D128558
[BOLT][TEST] Fix stack alignment in section-reloc-with-addend.sMisaligned stack can cause a runtime crash.Reviewed By: AmirDifferential Revision: https://reviews.llvm.org/D128227
[BOLT] Split functions with exceptions in shared objects and PIEsAdd functionality to allow splitting code with C++ exceptions in sharedlibraries and PIEs. To overcome a limitation in exception ra
[BOLT] Split functions with exceptions in shared objects and PIEsAdd functionality to allow splitting code with C++ exceptions in sharedlibraries and PIEs. To overcome a limitation in exception ranges format,for functions with fragments spanning multiple sections, add trampolinelanding pads in the same section as the corresponding throwing range.Reviewed By: AmirDifferential Revision: https://reviews.llvm.org/D127936
[BOLT][TEST] Use double dash flags in testsReplace a single dash with a double dash for options that have morethan a single letter.llvm-bolt-wrapper.py has special treatment for output options s
[BOLT][TEST] Use double dash flags in testsReplace a single dash with a double dash for options that have morethan a single letter.llvm-bolt-wrapper.py has special treatment for output options such as"-o" and "-w" causing issues when a single dash is used, e.g. for"-write-dwp". The wrapper can be fixed as well, but using a double dashhas other advantages as well.Reviewed By: rafaulerDifferential Revision: https://reviews.llvm.org/D127538
[BOLT] Cache-Aware Tail DuplicationA new "cache-aware" strategy for tail duplication.Differential Revision: https://reviews.llvm.org/D123050
[BOLT][TEST] Replace cache+ option with ext-tspReplace "cache+" with "ext-tsp" in all BOLT testsTest Plan:```ninja check-boltgrep -rnw . -e "cache+"```no more tests containing "cache+""cach
[BOLT][TEST] Replace cache+ option with ext-tspReplace "cache+" with "ext-tsp" in all BOLT testsTest Plan:```ninja check-boltgrep -rnw . -e "cache+"```no more tests containing "cache+""cache+" and "ext-tsp" are aliasesReviewed By: rafaulerDifferential Revision: https://reviews.llvm.org/D126714
[BOLT] Fix r_aarch64_prelxx testThe relocation value is calculated using the formula S + A - P,the verification of the value is performed by inversely calculating the location addressReviewed By
[BOLT] Fix r_aarch64_prelxx testThe relocation value is calculated using the formula S + A - P,the verification of the value is performed by inversely calculating the location addressReviewed By: AmirDifferential Revision: https://reviews.llvm.org/D124270
[BOLT] Add R_AARCH64_PREL16/32/64 relocations supportReviewed By: yota9, rafaulerDifferential Revision: https://reviews.llvm.org/D122294
[BOLT] Update skipRelocation for aarch64The ld might relax ADRP+ADD or ADRP+LDR sequences to the ADR+NOP, addthe new case to the skipRelocation for aarch64.Vladislav Khmelevsky,Advanced Softwar
[BOLT] Update skipRelocation for aarch64The ld might relax ADRP+ADD or ADRP+LDR sequences to the ADR+NOP, addthe new case to the skipRelocation for aarch64.Vladislav Khmelevsky,Advanced Software Technology Lab, HuaweiDifferential Revision: https://reviews.llvm.org/D123334
[BOLT][TEST] Add -no-pie to two testsMissed these two tests in D123329 in a rebase.
[BOLT][TEST] Remove -no-pie from cflags/cxxflagsAlign with an upstream change D120305 to make PIE the default on linux-gnu.Add `-no-pie` to tests that require it.Reviewed By: maksfb, yota9Dif
[BOLT][TEST] Remove -no-pie from cflags/cxxflagsAlign with an upstream change D120305 to make PIE the default on linux-gnu.Add `-no-pie` to tests that require it.Reviewed By: maksfb, yota9Differential Revision: https://reviews.llvm.org/D123329
[BOLT] Fix two aarch64 teststls-lld test might be broken since compiler might optimize plt functioncall and use address directly from got table. The test is removed sinceplt-gnu-ld checks the sam
[BOLT] Fix two aarch64 teststls-lld test might be broken since compiler might optimize plt functioncall and use address directly from got table. The test is removed sinceplt-gnu-ld checks the same functionality + versioning symbol matching,no need to keep both of the tests.The toolchain might optimize relocations in runtime-relocs test, replacethe test compilation with yaml files.Differential Revision: https://reviews.llvm.org/D123332
[BOLT] Fix plt relocations symbol matchThe bfd linker adds the symbol versioning string to the symbol name in symtab.Skip the versioning part in order to find the registered PLT function.Vladisl
[BOLT] Fix plt relocations symbol matchThe bfd linker adds the symbol versioning string to the symbol name in symtab.Skip the versioning part in order to find the registered PLT function.Vladislav Khmelevsky,Advanced Software Technology Lab, HuaweiDifferential Revision: https://reviews.llvm.org/D122039
[BOLT] Align constant islands to 8 bytesAArch64 requires CI to be aligned to 8 bytes due to access instructionsrestrictions. E.g. the ldr with imm, where imm must be aligned to 8 bytes.Different
[BOLT] Align constant islands to 8 bytesAArch64 requires CI to be aligned to 8 bytes due to access instructionsrestrictions. E.g. the ldr with imm, where imm must be aligned to 8 bytes.Differential Revision: https://reviews.llvm.org/D122065
[BOLT] Handle ifuncs trampolines for aarch64The aarch64 uses the trampolines located in .iplt section, whichcontains plt-like trampolines on the value stored in .got. In this casewe don't have JU
[BOLT] Handle ifuncs trampolines for aarch64The aarch64 uses the trampolines located in .iplt section, whichcontains plt-like trampolines on the value stored in .got. In this casewe don't have JUMP_SLOT relocation, but we have a symbol that belongs toifunc trampoline, so use it and set set plt symbol for such functions.Vladislav Khmelevsky,Advanced Software Technology Lab, HuaweiDifferential Revision: https://reviews.llvm.org/D120850
[BOLT] Enable PLT analysis for aarch64This patch enables PLT analysis for aarch64. It is used by the staticrelocations in order to provide final symbol address of PLT entry for someinstructions l
[BOLT] Enable PLT analysis for aarch64This patch enables PLT analysis for aarch64. It is used by the staticrelocations in order to provide final symbol address of PLT entry for someinstructions like ADRP.Vladislav Khmelevsky,Advanced Software Technology Lab, HuaweiDifferential Revision: https://reviews.llvm.org/D118088
[BOLT] Update dynamic relocations from section relocationsThis patch changes patchELFAllocatableRelaSections from going throughold relocations sections and update the relocation offsets to emittin
[BOLT] Update dynamic relocations from section relocationsThis patch changes patchELFAllocatableRelaSections from going throughold relocations sections and update the relocation offsets to emittingthe relocations stored in binary sections. This is needed in case wewould like to remove and add dynamic relocations during BOLT work and itis used by golang support pass. Note: Currently we emit relocations inthe old sections, so the total number of them should be equal or lessof old number.Testing: No special tests are neeeded, since this patch does not fixanything or add new functionality (it only prepares to add). EveryPIC-compiled test binary will use this code and thus become a test.But just in case the aarch64 dynamic relocations tests were added.Vladislav Khmelevsky,Advanced Software Technology Lab, HuaweiReviewed By: maksfbDifferential Revision: https://reviews.llvm.org/D117612
[BOLT][TEST] Fix building some tests with clang-14 by passing -no-pieReviewed By: yota9Differential Revision: https://reviews.llvm.org/D118556
[BOLT][TEST] Update exceptions-instrumentation.testMatching an exact byte offset is fragile if a different version of compileris used (e.g. distro clang).Resolves an issue with running with BOLT_
[BOLT][TEST] Update exceptions-instrumentation.testMatching an exact byte offset is fragile if a different version of compileris used (e.g. distro clang).Resolves an issue with running with BOLT_CLANG_EXE + clang-12Reviewed By: maksfbDifferential Revision: https://reviews.llvm.org/D117440
[BOLT][TEST] Move exceptions-instrumentation.test to X86The aarch64 instrumentation is currently unsupported so the test is failing.Reviewed By: AmirDifferential Revision: https://reviews.llvm.
[BOLT][TEST] Move exceptions-instrumentation.test to X86The aarch64 instrumentation is currently unsupported so the test is failing.Reviewed By: AmirDifferential Revision: https://reviews.llvm.org/D117102
[BOLT][TEST] Fix runtime/X86/retpoline-synthetic.testSummary:Restructure the test to prevent command echo from getting to checkstatements.(cherry picked from FBD32635888)
[BOLT] Fix tailcall-traps and basic-instr tests on ubuntuSummary: These tests are failing on opensource ubuntu.(cherry picked from FBD32514489)
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