1//===-- VOPInstructions.td - Vector Instruction Definitions ---------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// dummies for outer let 10class LetDummies { 11 bit TRANS; 12 bit ReadsModeReg; 13 bit mayRaiseFPException; 14 bit isCommutable; 15 bit isConvertibleToThreeAddress; 16 bit isMoveImm; 17 bit isReMaterializable; 18 bit isAsCheapAsAMove; 19 bit VOPAsmPrefer32Bit; 20 bit FPDPRounding; 21 Predicate SubtargetPredicate; 22 string Constraints; 23 string DisableEncoding; 24 list<SchedReadWrite> SchedRW; 25 list<Register> Uses; 26 list<Register> Defs; 27} 28 29class VOP <string opName> { 30 string OpName = opName; 31} 32 33class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> : 34 InstSI <outs, ins, asm, pattern> { 35 36 let mayLoad = 0; 37 let mayStore = 0; 38 let hasSideEffects = 0; 39 let UseNamedOperandTable = 1; 40 let VALU = 1; 41 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 42} 43 44class VOP_Pseudo <string opName, string suffix, VOPProfile P, dag outs, dag ins, 45 string asm, list<dag> pattern> : 46 InstSI <outs, ins, asm, pattern>, 47 VOP <opName>, 48 SIMCInstr <opName#suffix, SIEncodingFamily.NONE> { 49 let isPseudo = 1; 50 let isCodeGenOnly = 1; 51 let UseNamedOperandTable = 1; 52 53 string Mnemonic = opName; 54 VOPProfile Pfl = P; 55 56 string AsmOperands; 57} 58 59class VOP3Common <dag outs, dag ins, string asm = "", 60 list<dag> pattern = [], bit HasMods = 0> : 61 VOPAnyCommon <outs, ins, asm, pattern> { 62 63 // Using complex patterns gives VOP3 patterns a very high complexity rating, 64 // but standalone patterns are almost always preferred, so we need to adjust the 65 // priority lower. The goal is to use a high number to reduce complexity to 66 // zero (or less than zero). 67 let AddedComplexity = -1000; 68 69 let VOP3 = 1; 70 71 let AsmVariantName = AMDGPUAsmVariants.VOP3; 72 let AsmMatchConverter = !if(HasMods, "cvtVOP3", ""); 73 74 let isCodeGenOnly = 0; 75 76 int Size = 8; 77 78 // Because SGPRs may be allowed if there are multiple operands, we 79 // need a post-isel hook to insert copies in order to avoid 80 // violating constant bus requirements. 81 let hasPostISelHook = 1; 82} 83 84class VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern = [], 85 bit isVOP3P = 0, bit isVop3OpSel = 0> : 86 VOP_Pseudo <opName, "_e64", P, P.Outs64, 87 !if(isVop3OpSel, 88 P.InsVOP3OpSel, 89 !if(!and(isVOP3P, P.IsPacked), P.InsVOP3P, P.Ins64)), 90 "", pattern> { 91 92 let VOP3_OPSEL = isVop3OpSel; 93 let IsPacked = P.IsPacked; 94 let IsMAI = P.IsMAI; 95 96 let AsmOperands = !if(isVop3OpSel, 97 P.AsmVOP3OpSel, 98 !if(!and(isVOP3P, P.IsPacked), P.AsmVOP3P, P.Asm64)); 99 100 let Size = 8; 101 let mayLoad = 0; 102 let mayStore = 0; 103 let hasSideEffects = 0; 104 105 // Because SGPRs may be allowed if there are multiple operands, we 106 // need a post-isel hook to insert copies in order to avoid 107 // violating constant bus requirements. 108 let hasPostISelHook = 1; 109 110 // Using complex patterns gives VOP3 patterns a very high complexity rating, 111 // but standalone patterns are almost always preferred, so we need to adjust the 112 // priority lower. The goal is to use a high number to reduce complexity to 113 // zero (or less than zero). 114 let AddedComplexity = -1000; 115 116 let VOP3 = 1; 117 let VALU = 1; 118 let FPClamp = P.HasFPClamp; 119 let IntClamp = P.HasIntClamp; 120 let ClampLo = P.HasClampLo; 121 let ClampHi = P.HasClampHi; 122 123 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret); 124 125 let mayRaiseFPException = ReadsModeReg; 126 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 127 128 let AsmVariantName = AMDGPUAsmVariants.VOP3; 129 let AsmMatchConverter = 130 !if(isVOP3P, 131 "cvtVOP3P", 132 !if(!or(P.HasModifiers, P.HasOMod, P.HasIntClamp), 133 "cvtVOP3", 134 "")); 135} 136 137class VOP3P_Pseudo <string opName, VOPProfile P, list<dag> pattern = []> : 138 VOP3_Pseudo<opName, P, pattern, 1> { 139 let VOP3P = 1; 140} 141 142class VOP_Real<VOP_Pseudo ps> { 143 Instruction Opcode = !cast<Instruction>(NAME); 144 bit IsSingle = ps.Pfl.IsSingle; 145} 146 147class VOP3_Real <VOP_Pseudo ps, int EncodingFamily, string asm_name = ps.Mnemonic> : 148 VOP_Real <ps>, 149 InstSI <ps.OutOperandList, ps.InOperandList, asm_name # ps.AsmOperands, []>, 150 SIMCInstr <ps.PseudoInstr, EncodingFamily> { 151 152 let VALU = 1; 153 let VOP3 = 1; 154 let isPseudo = 0; 155 let isCodeGenOnly = 0; 156 let UseNamedOperandTable = 1; 157 158 // copy relevant pseudo op flags 159 let SubtargetPredicate = ps.SubtargetPredicate; 160 let OtherPredicates = ps.OtherPredicates; 161 let AsmMatchConverter = ps.AsmMatchConverter; 162 let AsmVariantName = ps.AsmVariantName; 163 let Constraints = ps.Constraints; 164 let DisableEncoding = ps.DisableEncoding; 165 let TSFlags = ps.TSFlags; 166 let UseNamedOperandTable = ps.UseNamedOperandTable; 167 let Uses = ps.Uses; 168 let Defs = ps.Defs; 169 let SchedRW = ps.SchedRW; 170 let mayLoad = ps.mayLoad; 171 let mayStore = ps.mayStore; 172 let TRANS = ps.TRANS; 173 174 VOPProfile Pfl = ps.Pfl; 175} 176 177// XXX - Is there any reason to distinguish this from regular VOP3 178// here? 179class VOP3P_Real<VOP_Pseudo ps, int EncodingFamily, string asm_name = ps.Mnemonic> : 180 VOP3_Real<ps, EncodingFamily, asm_name>; 181 182class VOP3a<VOPProfile P> : Enc64 { 183 bits<4> src0_modifiers; 184 bits<9> src0; 185 bits<3> src1_modifiers; 186 bits<9> src1; 187 bits<3> src2_modifiers; 188 bits<9> src2; 189 bits<1> clamp; 190 bits<2> omod; 191 192 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); 193 let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); 194 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); 195 196 let Inst{31-26} = 0x34; //encoding 197 let Inst{40-32} = !if(P.HasSrc0, src0, 0); 198 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 199 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 200 let Inst{60-59} = !if(P.HasOMod, omod, 0); 201 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 202 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); 203 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); 204} 205 206class VOP3a_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3a<p> { 207 let Inst{11} = !if(p.HasClamp, clamp{0}, 0); 208 let Inst{25-17} = op; 209} 210 211class VOP3a_gfx10<bits<10> op, VOPProfile p> : VOP3a<p> { 212 let Inst{15} = !if(p.HasClamp, clamp{0}, 0); 213 let Inst{25-16} = op; 214 let Inst{31-26} = 0x35; 215} 216 217class VOP3a_gfx11<bits<10> op, VOPProfile p> : VOP3a_gfx10<op, p>; 218 219class VOP3a_vi <bits<10> op, VOPProfile P> : VOP3a<P> { 220 let Inst{25-16} = op; 221 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 222} 223 224class VOP3e_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3a_gfx6_gfx7<op, p> { 225 bits<8> vdst; 226 let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0); 227} 228 229class VOP3e_gfx10<bits<10> op, VOPProfile p> : VOP3a_gfx10<op, p> { 230 bits<8> vdst; 231 let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0); 232} 233 234class VOP3e_gfx11<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p>; 235 236class VOP3e_vi <bits<10> op, VOPProfile P> : VOP3a_vi <op, P> { 237 bits<8> vdst; 238 let Inst{7-0} = !if(P.EmitDst, vdst{7-0}, 0); 239} 240 241class VOP3OpSel_gfx9 <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> { 242 let Inst{11} = !if(P.HasSrc0, src0_modifiers{2}, 0); 243 let Inst{12} = !if(P.HasSrc1, src1_modifiers{2}, 0); 244 let Inst{13} = !if(P.HasSrc2, src2_modifiers{2}, 0); 245 let Inst{14} = !if(P.HasDst, src0_modifiers{3}, 0); 246} 247 248class VOP3OpSel_gfx10<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> { 249 let Inst{11} = !if(p.HasSrc0, src0_modifiers{2}, 0); 250 let Inst{12} = !if(p.HasSrc1, src1_modifiers{2}, 0); 251 let Inst{13} = !if(p.HasSrc2, src2_modifiers{2}, 0); 252 let Inst{14} = !if(p.HasDst, src0_modifiers{3}, 0); 253} 254 255class VOP3OpSel_gfx11<bits<10> op, VOPProfile p> : VOP3OpSel_gfx10<op, p>; 256 257 258// NB: For V_INTERP* opcodes, src0 is encoded as src1 and vice versa 259class VOP3Interp_vi <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> { 260 bits<2> attrchan; 261 bits<6> attr; 262 bits<1> high; 263 264 let Inst{8} = 0; // No modifiers for src0 265 let Inst{61} = 0; 266 267 let Inst{9} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); 268 let Inst{62} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 269 270 let Inst{37-32} = attr; 271 let Inst{39-38} = attrchan; 272 let Inst{40} = !if(P.HasHigh, high, 0); 273 274 let Inst{49-41} = src0; 275} 276 277class VOP3Interp_gfx10<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> { 278 bits<6> attr; 279 bits<2> attrchan; 280 bits<1> high; 281 282 let Inst{8} = 0; 283 let Inst{9} = !if(p.HasSrc0Mods, src0_modifiers{1}, 0); 284 let Inst{37-32} = attr; 285 let Inst{39-38} = attrchan; 286 let Inst{40} = !if(p.HasHigh, high, 0); 287 let Inst{49-41} = src0; 288 let Inst{61} = 0; 289 let Inst{62} = !if(p.HasSrc0Mods, src0_modifiers{0}, 0); 290} 291 292class VOP3Interp_gfx11<bits<10> op, VOPProfile p> : VOP3Interp_gfx10<op, p>; 293 294class VOP3be <VOPProfile P> : Enc64 { 295 bits<8> vdst; 296 bits<2> src0_modifiers; 297 bits<9> src0; 298 bits<2> src1_modifiers; 299 bits<9> src1; 300 bits<2> src2_modifiers; 301 bits<9> src2; 302 bits<7> sdst; 303 bits<2> omod; 304 305 let Inst{7-0} = vdst; 306 let Inst{14-8} = sdst; 307 let Inst{31-26} = 0x34; //encoding 308 let Inst{40-32} = !if(P.HasSrc0, src0, 0); 309 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 310 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 311 let Inst{60-59} = !if(P.HasOMod, omod, 0); 312 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 313 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); 314 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); 315} 316 317class VOP3Pe <bits<7> op, VOPProfile P> : Enc64 { 318 bits<8> vdst; 319 bits<4> src0_modifiers; 320 bits<9> src0; 321 bits<4> src1_modifiers; 322 bits<9> src1; 323 bits<4> src2_modifiers; 324 bits<9> src2; 325 bits<1> clamp; 326 327 let Inst{7-0} = vdst; 328 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // neg_hi src0 329 let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); // neg_hi src1 330 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); // neg_hi src2 331 332 let Inst{11} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{2}, 0); // op_sel(0) 333 let Inst{12} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{2}, 0); // op_sel(1) 334 let Inst{13} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{2}, 0); // op_sel(2) 335 336 let Inst{14} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{3}, ?); // op_sel_hi(2) 337 338 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 339 340 let Inst{22-16} = op; 341 let Inst{31-23} = 0x1a7; //encoding 342 let Inst{40-32} = !if(P.HasSrc0, src0, 0); 343 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 344 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 345 let Inst{59} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{3}, ?); // op_sel_hi(0) 346 let Inst{60} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{3}, ?); // op_sel_hi(1) 347 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // neg (lo) 348 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // neg (lo) 349 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); // neg (lo) 350} 351 352class VOP3Pe_MAI <bits<7> op, VOPProfile P, bit acc_cd = 0> : Enc64 { 353 bits<8> vdst; 354 bits<10> src0; 355 bits<10> src1; 356 bits<9> src2; 357 bits<3> blgp; 358 bits<3> cbsz; 359 bits<4> abid; 360 361 let Inst{7-0} = vdst; 362 363 let Inst{10-8} = !if(P.HasSrc1, cbsz, 0); 364 let Inst{14-11} = !if(P.HasSrc1, abid, 0); 365 366 let Inst{15} = acc_cd; 367 368 let Inst{22-16} = op; 369 let Inst{31-23} = 0x1a7; //encoding 370 let Inst{40-32} = !if(P.HasSrc0, src0{8-0}, 0); 371 let Inst{49-41} = !if(P.HasSrc1, src1{8-0}, 0); 372 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 373 374 let Inst{59} = !if(P.HasSrc0, src0{9}, 0); // acc(0) 375 let Inst{60} = !if(P.HasSrc1, src1{9}, 0); // acc(1) 376 377 let Inst{63-61} = !if(P.HasSrc1, blgp, 0); 378} 379 380class VOP3Pe_SMFMAC <bits<7> op> : Enc64 { 381 bits<10> vdst; // VGPR or AGPR, but not SGPR. vdst{8} is not encoded in the instruction. 382 bits<10> src0; 383 bits<10> src1; 384 bits<9> idx; 385 bits<3> blgp; 386 bits<3> cbsz; 387 bits<4> abid; 388 389 let blgp = 0; 390 391 let Inst{7-0} = vdst{7-0}; 392 393 let Inst{10-8} = cbsz; 394 let Inst{14-11} = abid; 395 396 let Inst{15} = vdst{9}; // acc(vdst) 397 398 let Inst{22-16} = op; 399 let Inst{31-23} = 0x1a7; // encoding 400 let Inst{40-32} = src0{8-0}; 401 let Inst{49-41} = src1{8-0}; 402 let Inst{58-50} = idx; 403 404 let Inst{59} = src0{9}; // acc(0) 405 let Inst{60} = src1{9}; // acc(1) 406 407 let Inst{63-61} = blgp; 408} 409 410class VOP3Pe_gfx10 <bits<7> op, VOPProfile P> : VOP3Pe<op, P> { 411 let Inst{31-23} = 0x198; //encoding 412} 413 414class VOP3Pe_gfx11<bits<7> op, VOPProfile P> : VOP3Pe_gfx10<op, P>; 415 416class VOP3be_gfx6_gfx7<bits<9> op, VOPProfile p> : VOP3be<p> { 417 let Inst{25-17} = op; 418} 419 420class VOP3be_gfx10<bits<10> op, VOPProfile p> : VOP3be<p> { 421 bits<1> clamp; 422 let Inst{15} = !if(p.HasClamp, clamp{0}, 0); 423 let Inst{25-16} = op; 424 let Inst{31-26} = 0x35; 425} 426 427class VOP3be_gfx11<bits<10> op, VOPProfile p> : VOP3be_gfx10<op, p>; 428 429class VOP3be_vi <bits<10> op, VOPProfile P> : VOP3be<P> { 430 bits<1> clamp; 431 let Inst{25-16} = op; 432 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 433} 434 435def SDWA { 436 // sdwa_sel 437 int BYTE_0 = 0; 438 int BYTE_1 = 1; 439 int BYTE_2 = 2; 440 int BYTE_3 = 3; 441 int WORD_0 = 4; 442 int WORD_1 = 5; 443 int DWORD = 6; 444 445 // dst_unused 446 int UNUSED_PAD = 0; 447 int UNUSED_SEXT = 1; 448 int UNUSED_PRESERVE = 2; 449} 450 451class VOP_SDWAe<VOPProfile P> : Enc64 { 452 bits<8> src0; 453 bits<3> src0_sel; 454 bits<2> src0_modifiers; // float: {abs,neg}, int {sext} 455 bits<3> src1_sel; 456 bits<2> src1_modifiers; 457 bits<3> dst_sel; 458 bits<2> dst_unused; 459 bits<1> clamp; 460 461 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 462 let Inst{42-40} = !if(P.EmitDstSel, dst_sel{2-0}, ?); 463 let Inst{44-43} = !if(P.EmitDstSel, dst_unused{1-0}, ?); 464 let Inst{45} = !if(P.HasSDWAClamp, clamp{0}, 0); 465 let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, 0); 466 let Inst{51} = !if(P.HasSrc0IntMods, src0_modifiers{0}, 0); 467 let Inst{53-52} = !if(P.HasSrc0FloatMods, src0_modifiers{1-0}, 0); 468 let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0); 469 let Inst{59} = !if(P.HasSrc1IntMods, src1_modifiers{0}, 0); 470 let Inst{61-60} = !if(P.HasSrc1FloatMods, src1_modifiers{1-0}, 0); 471} 472 473// GFX9 adds two features to SDWA: 474// 1. Add 3 fields to the SDWA microcode word: S0, S1 and OMOD. 475// a. S0 and S1 indicate that source 0 and 1 respectively are SGPRs rather 476// than VGPRs (at most 1 can be an SGPR); 477// b. OMOD is the standard output modifier (result *2, *4, /2) 478// 2. Add a new version of the SDWA microcode word for VOPC: SDWAB. This 479// replaces OMOD and the dest fields with SD and SDST (SGPR destination) 480// field. 481// a. When SD=1, the SDST is used as the destination for the compare result; 482// b. When SD=0, VCC is used. 483// 484// In GFX9, V_MAC_F16, V_MAC_F32 opcodes cannot be used with SDWA 485 486// gfx9 SDWA basic encoding 487class VOP_SDWA9e<VOPProfile P> : Enc64 { 488 bits<9> src0; // {src0_sgpr{0}, src0{7-0}} 489 bits<3> src0_sel; 490 bits<2> src0_modifiers; // float: {abs,neg}, int {sext} 491 bits<3> src1_sel; 492 bits<2> src1_modifiers; 493 bits<1> src1_sgpr; 494 495 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 496 let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, 0); 497 let Inst{51} = !if(P.HasSrc0IntMods, src0_modifiers{0}, 0); 498 let Inst{53-52} = !if(P.HasSrc0FloatMods, src0_modifiers{1-0}, 0); 499 let Inst{55} = !if(P.HasSrc0, src0{8}, 0); 500 let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0); 501 let Inst{59} = !if(P.HasSrc1IntMods, src1_modifiers{0}, 0); 502 let Inst{61-60} = !if(P.HasSrc1FloatMods, src1_modifiers{1-0}, 0); 503 let Inst{63} = 0; // src1_sgpr - should be specified in subclass 504} 505 506// gfx9 SDWA-A 507class VOP_SDWA9Ae<VOPProfile P> : VOP_SDWA9e<P> { 508 bits<3> dst_sel; 509 bits<2> dst_unused; 510 bits<1> clamp; 511 bits<2> omod; 512 513 let Inst{42-40} = !if(P.EmitDstSel, dst_sel{2-0}, ?); 514 let Inst{44-43} = !if(P.EmitDstSel, dst_unused{1-0}, ?); 515 let Inst{45} = !if(P.HasSDWAClamp, clamp{0}, 0); 516 let Inst{47-46} = !if(P.HasSDWAOMod, omod{1-0}, 0); 517} 518 519// gfx9 SDWA-B 520class VOP_SDWA9Be<VOPProfile P> : VOP_SDWA9e<P> { 521 bits<8> sdst; // {vcc_sdst{0}, sdst{6-0}} 522 523 let Inst{46-40} = !if(P.EmitDst, sdst{6-0}, ?); 524 let Inst{47} = !if(P.EmitDst, sdst{7}, 0); 525} 526 527class VOP_SDWA_Pseudo <string opName, VOPProfile P, list<dag> pattern=[]> : 528 InstSI <P.OutsSDWA, P.InsSDWA, "", pattern>, 529 VOP <opName>, 530 SIMCInstr <opName#"_sdwa", SIEncodingFamily.NONE> { 531 532 let isPseudo = 1; 533 let isCodeGenOnly = 1; 534 let UseNamedOperandTable = 1; 535 536 string Mnemonic = opName; 537 string AsmOperands = P.AsmSDWA; 538 string AsmOperands9 = P.AsmSDWA9; 539 540 let Size = 8; 541 let mayLoad = 0; 542 let mayStore = 0; 543 let hasSideEffects = 0; 544 545 let VALU = 1; 546 let SDWA = 1; 547 548 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret); 549 550 let mayRaiseFPException = ReadsModeReg; 551 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 552 553 let SubtargetPredicate = HasSDWA; 554 let AssemblerPredicate = HasSDWA; 555 let AsmVariantName = !if(P.HasExtSDWA, AMDGPUAsmVariants.SDWA, 556 AMDGPUAsmVariants.Disable); 557 let DecoderNamespace = "SDWA"; 558 559 VOPProfile Pfl = P; 560} 561 562class VOP_SDWA_Real <VOP_SDWA_Pseudo ps> : 563 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>, 564 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA> { 565 566 let VALU = 1; 567 let SDWA = 1; 568 let isPseudo = 0; 569 let isCodeGenOnly = 0; 570 571 let Defs = ps.Defs; 572 let Uses = ps.Uses; 573 let hasSideEffects = ps.hasSideEffects; 574 575 let Constraints = ps.Constraints; 576 let DisableEncoding = ps.DisableEncoding; 577 578 // Copy relevant pseudo op flags 579 let SubtargetPredicate = ps.SubtargetPredicate; 580 let AssemblerPredicate = ps.AssemblerPredicate; 581 let AsmMatchConverter = ps.AsmMatchConverter; 582 let AsmVariantName = ps.AsmVariantName; 583 let UseNamedOperandTable = ps.UseNamedOperandTable; 584 let DecoderNamespace = ps.DecoderNamespace; 585 let Constraints = ps.Constraints; 586 let DisableEncoding = ps.DisableEncoding; 587 let TSFlags = ps.TSFlags; 588 let SchedRW = ps.SchedRW; 589 let mayLoad = ps.mayLoad; 590 let mayStore = ps.mayStore; 591 let TRANS = ps.TRANS; 592} 593 594class Base_VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> : 595 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands9, []> { 596 597 let VALU = 1; 598 let SDWA = 1; 599 let isPseudo = 0; 600 let isCodeGenOnly = 0; 601 602 let Defs = ps.Defs; 603 let Uses = ps.Uses; 604 let hasSideEffects = ps.hasSideEffects; 605 606 let Constraints = ps.Constraints; 607 let DisableEncoding = ps.DisableEncoding; 608 609 let SubtargetPredicate = HasSDWA9; 610 let AssemblerPredicate = HasSDWA9; 611 let AsmVariantName = !if(ps.Pfl.HasExtSDWA9, AMDGPUAsmVariants.SDWA9, 612 AMDGPUAsmVariants.Disable); 613 let DecoderNamespace = "SDWA9"; 614 615 // Copy relevant pseudo op flags 616 let AsmMatchConverter = ps.AsmMatchConverter; 617 let UseNamedOperandTable = ps.UseNamedOperandTable; 618 let Constraints = ps.Constraints; 619 let DisableEncoding = ps.DisableEncoding; 620 let TSFlags = ps.TSFlags; 621 let SchedRW = ps.SchedRW; 622 let mayLoad = ps.mayLoad; 623 let mayStore = ps.mayStore; 624 let TRANS = ps.TRANS; 625} 626 627class VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> : 628 Base_VOP_SDWA9_Real <ps >, 629 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA9>; 630 631class Base_VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> : Base_VOP_SDWA9_Real<ps> { 632 let SubtargetPredicate = HasSDWA10; 633 let AssemblerPredicate = HasSDWA10; 634 let DecoderNamespace = "SDWA10"; 635} 636 637class VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> : 638 Base_VOP_SDWA10_Real<ps>, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SDWA10>; 639 640class VOP_DPPe<VOPProfile P, bit IsDPP16=0> : Enc64 { 641 bits<2> src0_modifiers; 642 bits<8> src0; 643 bits<2> src1_modifiers; 644 bits<9> dpp_ctrl; 645 bits<1> bound_ctrl; 646 bits<4> bank_mask; 647 bits<4> row_mask; 648 bit fi; 649 650 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 651 let Inst{48-40} = dpp_ctrl; 652 let Inst{50} = !if(IsDPP16, fi, ?); 653 let Inst{51} = bound_ctrl; 654 let Inst{52} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // src0_neg 655 let Inst{53} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // src0_abs 656 let Inst{54} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // src1_neg 657 let Inst{55} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); // src1_abs 658 let Inst{59-56} = bank_mask; 659 let Inst{63-60} = row_mask; 660} 661 662class VOP3_DPPe_Fields_Base { 663 bits<9> dpp_ctrl; 664 bits<1> bound_ctrl; 665 bits<4> bank_mask; 666 bits<4> row_mask; 667 bit fi; 668} 669class VOP3_DPPe_Fields : VOP3_DPPe_Fields_Base { 670 bits<8> src0; 671} 672 673// Common refers to common between DPP and DPP8 674class VOP3_DPPe_Common_Base<bits<10> op, VOPProfile P> : Enc96 { 675 bits<4> src0_modifiers; 676 bits<3> src1_modifiers; 677 bits<3> src2_modifiers; 678 bits<1> clamp; 679 bits<2> omod; 680 681 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); 682 let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); 683 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); 684 // OPSEL must be set such that the low result only uses low inputs, and the high result only uses high inputs. 685 let Inst{11} = !if(P.HasOpSel,!if(P.HasSrc0Mods, src0_modifiers{2}, 0),?); 686 let Inst{12} = !if(P.HasOpSel,!if(P.HasSrc1Mods, src1_modifiers{2}, 0),?); 687 let Inst{13} = !if(P.HasOpSel,!if(P.HasSrc2Mods, src2_modifiers{2}, 0),?); 688 let Inst{14} = !if(P.HasOpSel,!if(P.HasSrc0Mods, src0_modifiers{3}, 0),?); 689 let Inst{15} = !if(P.HasClamp, clamp, 0); 690 let Inst{25-16} = op; 691 let Inst{31-26} = 0x35; 692 693 let Inst{60-59} = !if(P.HasOMod, omod, 0); 694 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); 695 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); 696 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); 697} 698 699class VOP3_DPPe_Common<bits<10> op, VOPProfile P> : VOP3_DPPe_Common_Base<op, P> { 700 bits<8> vdst; 701 bits<9> src1; 702 bits<9> src2; 703 704 let Inst{7-0} = !if(P.EmitDst, vdst{7-0}, 0); 705 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 706 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 707} 708 709class VOP3P_DPPe_Common_Base<bits<7> op, VOPProfile P> : Enc96 { 710 bits<4> src0_modifiers; 711 bits<4> src1_modifiers; 712 bits<4> src2_modifiers; 713 bits<1> clamp; 714 715 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // neg_hi src0 716 let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); // neg_hi src1 717 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); // neg_hi src2 718 let Inst{11} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{2}, 0); // op_sel(0) 719 let Inst{12} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{2}, 0); // op_sel(1) 720 let Inst{13} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{2}, 0); // op_sel(2) 721 let Inst{14} = !if(!and(P.HasSrc2, P.HasOpSel), src2_modifiers{3}, ?); // op_sel_hi(2) 722 let Inst{15} = !if(P.HasClamp, clamp{0}, 0); 723 let Inst{22-16} = op; 724 let Inst{31-23} = 0x198; // encoding 725 let Inst{59} = !if(!and(P.HasSrc0, P.HasOpSel), src0_modifiers{3}, ?); // op_sel_hi(0) 726 let Inst{60} = !if(!and(P.HasSrc1, P.HasOpSel), src1_modifiers{3}, ?); // op_sel_hi(1) 727 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0); // neg (lo) 728 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0); // neg (lo) 729 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0); // neg (lo) 730} 731 732class VOP3P_DPPe_Common<bits<7> op, VOPProfile P> : VOP3P_DPPe_Common_Base<op, P> { 733 bits<8> vdst; 734 bits<9> src1; 735 bits<9> src2; 736 737 let Inst{7-0} = vdst; 738 let Inst{49-41} = !if(P.HasSrc1, src1, 0); 739 let Inst{58-50} = !if(P.HasSrc2, src2, 0); 740} 741 742class VOP_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[], 743 dag Ins = P.InsDPP, string asmOps = P.AsmDPP> : 744 InstSI <P.OutsDPP, Ins, OpName#asmOps, pattern>, 745 VOP <OpName>, 746 SIMCInstr <OpName#"_dpp", SIEncodingFamily.NONE> { 747 748 let isPseudo = 1; 749 let isCodeGenOnly = 1; 750 751 let mayLoad = 0; 752 let mayStore = 0; 753 let hasSideEffects = 0; 754 let UseNamedOperandTable = 1; 755 756 let VALU = 1; 757 let DPP = 1; 758 let Size = 8; 759 760 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret); 761 762 let mayRaiseFPException = ReadsModeReg; 763 let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]); 764 let isConvergent = 1; 765 766 string Mnemonic = OpName; 767 string AsmOperands = asmOps; 768 769 let AsmMatchConverter = !if(P.HasModifiers, "cvtDPP", ""); 770 let SubtargetPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 771 let AssemblerPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 772 let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP, 773 AMDGPUAsmVariants.Disable); 774 let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", ""); 775 let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, ""); 776 let DecoderNamespace = "DPP"; 777 778 VOPProfile Pfl = P; 779} 780 781class VOP3_DPP_Pseudo <string OpName, VOPProfile P> : 782 VOP_DPP_Pseudo <OpName, P, [], P.InsVOP3DPP, P.AsmVOP3DPP> { 783 let PseudoInstr = OpName#"_e64"#"_dpp"; 784 let OutOperandList = P.OutsVOP3DPP; 785 let Size = 12; 786 let VOP3 = 1; 787 let AsmMatchConverter = "cvtVOP3DPP"; 788 let AsmVariantName = !if(P.HasExtVOP3DPP, AMDGPUAsmVariants.VOP3_DPP, 789 AMDGPUAsmVariants.Disable); 790} 791 792class VOP_DPP_Real <VOP_DPP_Pseudo ps, int EncodingFamily> : 793 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>, 794 SIMCInstr <ps.PseudoInstr, EncodingFamily> { 795 796 let VALU = 1; 797 let DPP = 1; 798 let isPseudo = 0; 799 let isCodeGenOnly = 0; 800 801 let Defs = ps.Defs; 802 let Uses = ps.Uses; 803 let hasSideEffects = ps.hasSideEffects; 804 805 let Constraints = ps.Constraints; 806 let DisableEncoding = ps.DisableEncoding; 807 808 // Copy relevant pseudo op flags 809 let isConvergent = ps.isConvergent; 810 let SubtargetPredicate = ps.SubtargetPredicate; 811 let AssemblerPredicate = ps.AssemblerPredicate; 812 let OtherPredicates = ps.OtherPredicates; 813 let AsmMatchConverter = ps.AsmMatchConverter; 814 let AsmVariantName = ps.AsmVariantName; 815 let UseNamedOperandTable = ps.UseNamedOperandTable; 816 let DecoderNamespace = ps.DecoderNamespace; 817 let Constraints = ps.Constraints; 818 let DisableEncoding = ps.DisableEncoding; 819 let TSFlags = ps.TSFlags; 820 let SchedRW = ps.SchedRW; 821 let mayLoad = ps.mayLoad; 822 let mayStore = ps.mayStore; 823 let TRANS = ps.TRANS; 824} 825 826class VOP_DPP_Base <string OpName, VOPProfile P, 827 dag InsDPP, 828 string AsmDPP > : 829 InstSI <P.OutsDPP, InsDPP, OpName#AsmDPP, []> { 830 831 let mayLoad = 0; 832 let mayStore = 0; 833 let hasSideEffects = 0; 834 let UseNamedOperandTable = 1; 835 836 let VALU = 1; 837 let DPP = 1; 838 let Size = 8; 839 840 let AsmMatchConverter = !if(P.HasModifiers, "cvtDPP", ""); 841 let SubtargetPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 842 let AssemblerPredicate = !if(P.HasExt64BitDPP, Has64BitDPP, HasDPP); 843 let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP, 844 AMDGPUAsmVariants.Disable); 845 let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", ""); 846 let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, ""); 847 let DecoderNamespace = "DPP"; 848} 849 850class VOP_DPP <string OpName, VOPProfile P, bit IsDPP16, 851 dag InsDPP = !if(IsDPP16, P.InsDPP16, P.InsDPP), 852 string AsmDPP = !if(IsDPP16, P.AsmDPP16, P.AsmDPP)> : 853 VOP_DPP_Base<OpName, P, InsDPP, AsmDPP>, VOP_DPPe<P, IsDPP16>; 854 855class VOP3_DPP_Base <string OpName, VOPProfile P, bit IsDPP16, 856 dag InsDPP = !if(IsDPP16, P.InsVOP3DPP16, P.InsVOP3DPP), 857 string AsmDPP = !if(IsDPP16, P.AsmVOP3DPP16, P.AsmVOP3DPP)> : 858 VOP_DPP_Base<OpName, P, InsDPP, AsmDPP> { 859 let OutOperandList = P.OutsVOP3DPP; 860 let AsmMatchConverter = "cvtVOP3DPP"; 861 let VOP3 = 1; 862 let AsmVariantName = !if(P.HasExtVOP3DPP, AMDGPUAsmVariants.VOP3_DPP, 863 AMDGPUAsmVariants.Disable); 864 let Size = 12; 865} 866 867class VOP3_DPP <bits<10> op, string OpName, VOPProfile P, bit IsDPP16, 868 dag InsDPP = !if(IsDPP16, P.InsVOP3DPP16, P.InsVOP3DPP), 869 string AsmDPP = !if(IsDPP16, P.AsmVOP3DPP16, P.AsmVOP3DPP)> : 870 VOP3_DPP_Base<OpName, P, IsDPP16, InsDPP, AsmDPP>, VOP3_DPPe_Common<op, P>, 871 VOP3_DPPe_Fields { 872 873 let Inst{40-32} = 0xfa; 874 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0); 875 let Inst{80-72} = dpp_ctrl; 876 let Inst{82} = !if(IsDPP16, fi, ?); 877 let Inst{83} = bound_ctrl; 878 879 // Inst{87-84} ignored by hw 880 let Inst{91-88} = bank_mask; 881 let Inst{95-92} = row_mask; 882} 883 884class VOP3P_DPP <bits<7> op, string OpName, VOPProfile P, bit IsDPP16, 885 dag InsDPP = !if(IsDPP16, P.InsVOP3DPP16, P.InsVOP3DPP), 886 string AsmDPP = !if(IsDPP16, P.AsmVOP3DPP16, P.AsmVOP3DPP)> : 887 VOP3_DPP_Base<OpName, P, IsDPP16, InsDPP, AsmDPP>, VOP3P_DPPe_Common<op, P>, 888 VOP3_DPPe_Fields { 889 890 let VOP3P = 1; 891 892 let Inst{40-32} = 0xfa; 893 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0); 894 let Inst{80-72} = dpp_ctrl; 895 let Inst{82} = !if(IsDPP16, fi, ?); 896 let Inst{83} = bound_ctrl; 897 898 // Inst{87-84} ignored by hw 899 let Inst{91-88} = bank_mask; 900 let Inst{95-92} = row_mask; 901} 902 903class VOP_DPP8e<VOPProfile P> : Enc64 { 904 bits<8> src0; 905 bits<24> dpp8; 906 bits<9> fi; 907 908 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); 909 let Inst{63-40} = dpp8{23-0}; 910} 911 912class VOP3_DPP8e_Fields { 913 bits<8> src0; 914 bits<24> dpp8; 915 bits<9> fi; 916} 917 918class VOP_DPP8_Base<string OpName, VOPProfile P, dag InsDPP8 = P.InsDPP8, string AsmDPP8 = P.AsmDPP8> : 919 InstSI<P.OutsDPP8, InsDPP8, OpName#AsmDPP8, []> { 920 921 let mayLoad = 0; 922 let mayStore = 0; 923 let hasSideEffects = 0; 924 let UseNamedOperandTable = 1; 925 926 let VALU = 1; 927 let DPP = 1; 928 let Size = 8; 929 930 let AsmMatchConverter = "cvtDPP8"; 931 let SubtargetPredicate = HasDPP8; 932 let AssemblerPredicate = HasDPP8; 933 let AsmVariantName = AMDGPUAsmVariants.DPP; 934 let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $vdst", ""); 935 let DisableEncoding = !if(P.NumSrcArgs, P.TieRegDPP, ""); 936} 937 938class VOP_DPP8<string OpName, VOPProfile P> : 939 VOP_DPP8_Base<OpName, P>, VOP_DPP8e<P>; 940 941class VOP3_DPP8_Base<string OpName, VOPProfile P> : 942 VOP_DPP8_Base<OpName, P, P.InsVOP3DPP8, P.AsmVOP3DPP8> { 943 let OutOperandList = P.OutsVOP3DPP8; 944 let AsmMatchConverter = "cvtVOP3DPP8"; 945 let AsmVariantName = !if(P.HasExtVOP3DPP, AMDGPUAsmVariants.VOP3_DPP, 946 AMDGPUAsmVariants.Disable); 947 let VOP3 = 1; 948 let Size = 12; 949} 950 951 952class VOP3_DPP8<bits<10> op, string OpName, VOPProfile P> : 953 VOP3_DPP8_Base<OpName, P>, VOP3_DPPe_Common<op, P>, 954 VOP3_DPP8e_Fields { 955 956 let Inst{40-32} = fi; 957 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0); 958 let Inst{95-72} = dpp8{23-0}; 959} 960 961class VOP3P_DPP8<bits<7> op, string OpName, VOPProfile P> : 962 VOP3_DPP8_Base<OpName, P>, VOP3P_DPPe_Common<op, P>, 963 VOP3_DPP8e_Fields { 964 965 let VOP3P = 1; 966 let Inst{40-32} = fi; 967 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0); 968 let Inst{95-72} = dpp8{23-0}; 969} 970 971def DPP8Mode { 972 int FI_0 = 0xE9; 973 int FI_1 = 0xEA; 974} 975 976class getNumNodeArgs<SDPatternOperator Op> { 977 SDNode N = !cast<SDNode>(Op); 978 SDTypeProfile TP = N.TypeProfile; 979 int ret = TP.NumOperands; 980} 981 982class getDivergentFrag<SDPatternOperator Op> { 983 assert !or(!isa<SDNode>(Op), !isa<PatFrags>(Op)), "Expected SDNode or PatFrags"; 984 985 int NumSrcArgs = !if(!isa<SDNode>(Op), getNumNodeArgs<Op>.ret, 986 !size(!cast<PatFrags>(Op).Operands)); 987 PatFrag ret = PatFrag < 988 !if(!eq(NumSrcArgs, 1), 989 (ops node:$src0), 990 !if(!eq(NumSrcArgs, 2), 991 (ops node:$src0, node:$src1), 992 (ops node:$src0, node:$src1, node:$src2))), 993 !if(!eq(NumSrcArgs, 1), 994 (Op $src0), 995 !if(!eq(NumSrcArgs, 2), 996 (Op $src0, $src1), 997 (Op $src0, $src1, $src2))), 998 [{ return N->isDivergent(); }] 999 >; 1000} 1001 1002class VOPPatGen<SDPatternOperator Op, VOPProfile P> { 1003 PatFrag Operator = getDivergentFrag < Op >.ret; 1004 1005 dag Ins = !foreach(tmp, P.Ins32, !subst(ins, Operator, 1006 !subst(P.Src0RC32, P.Src0VT, 1007 !subst(P.Src1RC32, P.Src1VT, tmp)))); 1008 1009 dag Outs = !foreach(tmp, P.Outs32, !subst(outs, set, 1010 !subst(P.DstRC, P.DstVT, tmp))); 1011 1012 list<dag> ret = [!con(Outs, (set Ins))]; 1013} 1014 1015class DivergentUnaryFrag<SDPatternOperator Op> : PatFrag < 1016 (ops node:$src0), 1017 (Op $src0), 1018 [{ return N->isDivergent(); }]> { 1019 // This check is unnecessary as it's captured by the result register 1020 // bank constraint. 1021 // 1022 // FIXME: Should add a way for the emitter to recognize this is a 1023 // trivially true predicate to eliminate the check. 1024 let GISelPredicateCode = [{return true;}]; 1025} 1026 1027class VOPPatOrNull<SDPatternOperator Op, VOPProfile P> { 1028 list<dag> ret = !if(!ne(P.NeedPatGen,PatGenMode.NoPattern), VOPPatGen<Op, P>.ret, []); 1029} 1030 1031class DivergentFragOrOp<SDPatternOperator Op, VOPProfile P> { 1032 SDPatternOperator ret = !if(!eq(P.NeedPatGen,PatGenMode.Pattern), 1033 !if(!isa<SDNode>(Op), getDivergentFrag<Op>.ret, Op), Op); 1034} 1035 1036class getVSrcOp<ValueType vt> { 1037 RegisterOperand ret = !if(!eq(vt.Size, 32), VSrc_b32, VSrc_b16); 1038} 1039 1040// Class for binary integer operations with the clamp bit set for saturation 1041// TODO: Add sub with negated inline constant pattern. 1042class VOPBinOpClampPat<SDPatternOperator node, Instruction inst, ValueType vt> : 1043 GCNPat<(node vt:$src0, vt:$src1), 1044 (inst getVSrcOp<vt>.ret:$src0, getVSrcOp<vt>.ret:$src1, 1045 DSTCLAMP.ENABLE) 1046>; 1047 1048//===----------------------------------------------------------------------===// 1049// VOP3 Classes 1050//===----------------------------------------------------------------------===// 1051 1052class getVOP3ModPat<VOPProfile P, SDPatternOperator node> { 1053 dag src0 = !if(P.HasOMod, 1054 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod), 1055 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)); 1056 1057 list<dag> ret3 = [(set P.DstVT:$vdst, 1058 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), 1059 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), 1060 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))]; 1061 1062 list<dag> ret2 = [(set P.DstVT:$vdst, 1063 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), 1064 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))]; 1065 1066 list<dag> ret1 = [(set P.DstVT:$vdst, 1067 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0)))]; 1068 1069 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 1070 !if(!eq(P.NumSrcArgs, 2), ret2, 1071 ret1)); 1072} 1073 1074class getVOP3PModPat<VOPProfile P, SDPatternOperator node, bit HasExplicitClamp, 1075 bit IsDOT = 0, 1076 ComplexPattern SrcPat = !if(IsDOT, VOP3PModsDOT, VOP3PMods)> { 1077 dag src0_dag = (P.Src0VT (SrcPat P.Src0VT:$src0, i32:$src0_modifiers)); 1078 dag src1_dag = (P.Src1VT (SrcPat P.Src1VT:$src1, i32:$src1_modifiers)); 1079 dag src2_dag = (P.Src2VT (SrcPat P.Src2VT:$src2, i32:$src2_modifiers)); 1080 dag clamp_dag = (i1 timm:$clamp); 1081 1082 list<dag> ret3 = [(set P.DstVT:$vdst, 1083 !if(HasExplicitClamp, 1084 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag, src2_dag, clamp_dag), 1085 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag, src2_dag)))]; 1086 1087 list<dag> ret2 = [(set P.DstVT:$vdst, 1088 !if(HasExplicitClamp, 1089 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag, clamp_dag), 1090 (DivergentFragOrOp<node, P>.ret src0_dag, src1_dag)))]; 1091 1092 list<dag> ret1 = [(set P.DstVT:$vdst, 1093 !if(HasExplicitClamp, 1094 (DivergentFragOrOp<node, P>.ret src0_dag, clamp_dag), 1095 (DivergentFragOrOp<node, P>.ret src0_dag)))]; 1096 1097 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 1098 !if(!eq(P.NumSrcArgs, 2), ret2, 1099 ret1)); 1100} 1101 1102class getVOP3OpSelPat<VOPProfile P, SDPatternOperator node> { 1103 list<dag> ret3 = [(set P.DstVT:$vdst, 1104 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers)), 1105 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers)), 1106 (P.Src2VT (VOP3OpSel P.Src2VT:$src2, i32:$src2_modifiers))))]; 1107 1108 list<dag> ret2 = [(set P.DstVT:$vdst, 1109 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers)), 1110 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers))))]; 1111 1112 list<dag> ret1 = [(set P.DstVT:$vdst, 1113 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))))]; 1114 1115 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 1116 !if(!eq(P.NumSrcArgs, 2), ret2, 1117 ret1)); 1118} 1119 1120class getVOP3OpSelModPat<VOPProfile P, SDPatternOperator node> { 1121 list<dag> ret3 = [(set P.DstVT:$vdst, 1122 (DivergentFragOrOp<node, P>.ret (P.Src0VT !if(P.HasClamp, (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers), 1123 (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))), 1124 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers)), 1125 (P.Src2VT (VOP3OpSelMods P.Src2VT:$src2, i32:$src2_modifiers))))]; 1126 1127 list<dag> ret2 = [(set P.DstVT:$vdst, 1128 (DivergentFragOrOp<node, P>.ret !if(P.HasClamp, (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers)), 1129 (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))), 1130 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers))))]; 1131 1132 list<dag> ret1 = [(set P.DstVT:$vdst, 1133 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))))]; 1134 1135 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 1136 !if(!eq(P.NumSrcArgs, 2), ret2, 1137 ret1)); 1138} 1139 1140class getVOP3FromVOP2Pat<VOPProfile P, SDPatternOperator node> { 1141 list<dag> ret = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]; 1142} 1143// In VOP1, we can have clamp and omod even if !HasModifiers 1144class getVOP3Pat<VOPProfile P, SDPatternOperator node> { 1145 dag src0 = 1146 !if(P.HasOMod, 1147 !if(P.HasClamp, 1148 (VOP3Mods0 P.Src0VT:$src0, i1:$clamp, i32:$omod), 1149 (VOP3Mods0 P.Src0VT:$src0, i32:$omod)), // impossible? 1150 !if(P.HasClamp, 1151 (VOP3Mods0 P.Src0VT:$src0, i1:$clamp), 1152 (VOP3Mods0 P.Src0VT:$src0)) 1153 ); 1154 list<dag> ret3 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), P.Src1VT:$src1, P.Src2VT:$src2))]; 1155 1156 list<dag> ret2 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), P.Src1VT:$src1))]; 1157 1158 list<dag> ret1 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret (P.Src0VT src0)))]; 1159 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 1160 !if(!eq(P.NumSrcArgs, 2), ret2, 1161 ret1)); 1162} 1163 1164class getVOP3ClampPat<VOPProfile P, SDPatternOperator node> { 1165 list<dag> ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, i1:$clamp))]; 1166 list<dag> ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, i1:$clamp))]; 1167 list<dag> ret1 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, i1:$clamp))]; 1168 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3, 1169 !if(!eq(P.NumSrcArgs, 2), ret2, 1170 ret1)); 1171} 1172 1173class getVOP3MAIPat<VOPProfile P, SDPatternOperator node> { 1174 list<dag> ret = !if(!eq(P.Src0VT, P.Src1VT), 1175 // mfma 1176 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, 1177 timm:$cbsz, timm:$abid, timm:$blgp))], 1178 // smfmac 1179 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, i32:$idx, 1180 timm:$cbsz, timm:$abid))]); 1181} 1182 1183class VOP3Features<bit Clamp, bit OpSel, bit Packed, bit MAI> { 1184 bit HasClamp = Clamp; 1185 bit HasOpSel = OpSel; 1186 bit IsPacked = Packed; 1187 bit IsMAI = MAI; 1188} 1189 1190def VOP3_REGULAR : VOP3Features<0, 0, 0, 0>; 1191def VOP3_CLAMP : VOP3Features<1, 0, 0, 0>; 1192def VOP3_OPSEL : VOP3Features<1, 1, 0, 0>; 1193def VOP3_PACKED : VOP3Features<1, 1, 1, 0>; 1194def VOP3_MAI : VOP3Features<0, 0, 0, 1>; 1195 1196class VOP3_Profile_Base<VOPProfile P, VOP3Features Features = VOP3_REGULAR> : VOPProfile<P.ArgVT> { 1197 1198 let HasClamp = !if(Features.HasClamp, 1, P.HasClamp); 1199 let HasOpSel = !if(Features.HasOpSel, 1, P.HasOpSel); 1200 let IsMAI = !if(Features.IsMAI, 1, P.IsMAI); 1201 let IsPacked = !if(Features.IsPacked, 1, P.IsPacked); 1202 1203 let HasModifiers = !if(Features.IsMAI, 0, !or(Features.IsPacked, P.HasModifiers)); 1204} 1205 1206class VOP3_Profile<VOPProfile P, VOP3Features Features = VOP3_REGULAR> : VOP3_Profile_Base<P, Features> { 1207 let IsSingle = 1; 1208 1209} 1210 1211// consistently gives instructions a _e64 suffix 1212multiclass VOP3Inst_Pseudo_Wrapper<string opName, VOPProfile P, list<dag> pattern = [], bit VOP3Only = 0> { 1213 def _e64 : VOP3_Pseudo<opName, P, pattern, VOP3Only>; 1214} 1215 1216class VOP3InstBase<string OpName, VOPProfile P, SDPatternOperator node = null_frag, bit IsVOP2 = 0> : 1217 VOP3_Pseudo<OpName, P, 1218 !if(P.HasOpSel, 1219 !if(P.HasModifiers, 1220 getVOP3OpSelModPat<P, node>.ret, 1221 getVOP3OpSelPat<P, node>.ret), 1222 !if(P.HasModifiers, 1223 getVOP3ModPat<P, node>.ret, 1224 !if(IsVOP2, 1225 getVOP3FromVOP2Pat<P, node>.ret, 1226 !if(P.HasIntClamp, 1227 getVOP3ClampPat<P, node>.ret, 1228 !if (P.IsMAI, 1229 getVOP3MAIPat<P, node>.ret, 1230 getVOP3Pat<P, node>.ret))))), 1231 0, P.HasOpSel> { 1232 1233 let IntClamp = P.HasIntClamp; 1234 let AsmMatchConverter = 1235 !if(P.HasOpSel, 1236 "cvtVOP3OpSel", 1237 !if(!or(P.HasModifiers, P.HasOMod, P.HasIntClamp), 1238 "cvtVOP3", 1239 "")); 1240} 1241 1242multiclass VOP3Inst<string OpName, VOPProfile P, SDPatternOperator node = null_frag> { 1243 def _e64 : VOP3InstBase<OpName, P, node>; 1244 let SubtargetPredicate = isGFX11Plus in { 1245 foreach _ = BoolToList<P.HasExtVOP3DPP>.ret in 1246 def _e64_dpp : VOP3_DPP_Pseudo <OpName, P>; 1247 } // end SubtargetPredicate = isGFX11Plus 1248} 1249 1250//===----------------------------------------------------------------------===// 1251// VOP3 DPP 1252//===----------------------------------------------------------------------===// 1253 1254class Base_VOP3_DPP16<bits<10> op, VOP_DPP_Pseudo ps, string opName = ps.OpName> 1255 : VOP3_DPP<op, opName, ps.Pfl, 1> { 1256 let hasSideEffects = ps.hasSideEffects; 1257 let Defs = ps.Defs; 1258 let SchedRW = ps.SchedRW; 1259 let Uses = ps.Uses; 1260 let AssemblerPredicate = HasDPP16; 1261 let SubtargetPredicate = HasDPP16; 1262 let OtherPredicates = ps.OtherPredicates; 1263} 1264 1265class VOP3_DPP16<bits<10> op, VOP_DPP_Pseudo ps, int subtarget, 1266 string opName = ps.OpName> 1267 : Base_VOP3_DPP16<op, ps, opName>, SIMCInstr<ps.PseudoInstr, subtarget>; 1268 1269class Base_VOP3_DPP8<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName> 1270 : VOP3_DPP8<op, opName, ps.Pfl> { 1271 let hasSideEffects = ps.hasSideEffects; 1272 let Defs = ps.Defs; 1273 let SchedRW = ps.SchedRW; 1274 let Uses = ps.Uses; 1275 1276 let OtherPredicates = ps.OtherPredicates; 1277} 1278 1279class Base_VOP3b_DPP16<bits<10> op, VOP_DPP_Pseudo ps, 1280 string opName = ps.OpName> 1281 : Base_VOP3_DPP16<op, ps, opName> { 1282 bits<7> sdst; 1283 let Inst{14 - 8} = sdst; 1284} 1285 1286class VOP3b_DPP8_Base<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName> 1287 : Base_VOP3_DPP8<op, ps, opName> { 1288 bits<7> sdst; 1289 let Inst{14 - 8} = sdst; 1290} 1291 1292//===----------------------------------------------------------------------===// 1293// VOP3 GFX11 1294//===----------------------------------------------------------------------===// 1295 1296let AssemblerPredicate = isGFX11Only, 1297 DecoderNamespace = "GFX11" in { 1298 multiclass VOP3_Real_Base_gfx11<bits<10> op, string opName = NAME, 1299 bit isSingle = 0> { 1300 defvar ps = !cast<VOP_Pseudo>(opName#"_e64"); 1301 let IsSingle = !or(isSingle, ps.Pfl.IsSingle) in { 1302 foreach _ = BoolToList<ps.Pfl.HasOpSel>.ret in 1303 def _e64_gfx11 : 1304 VOP3_Real<ps, SIEncodingFamily.GFX11>, 1305 VOP3OpSel_gfx11<op, ps.Pfl>; 1306 foreach _ = BoolToList<!not(ps.Pfl.HasOpSel)>.ret in 1307 def _e64_gfx11 : 1308 VOP3_Real<ps, SIEncodingFamily.GFX11>, 1309 VOP3e_gfx11<op, ps.Pfl>; 1310 } 1311 } 1312 multiclass VOP3_Real_with_name_gfx11<bits<10> op, string opName, 1313 string asmName, bit isSingle = 0> { 1314 defvar ps = !cast<VOP_Pseudo>(opName#"_e64"); 1315 let AsmString = asmName # ps.AsmOperands, 1316 IsSingle = !or(isSingle, ps.Pfl.IsSingle) in { 1317 foreach _ = BoolToList<ps.Pfl.HasOpSel>.ret in 1318 def _e64_gfx11 : 1319 VOP3_Real<ps, SIEncodingFamily.GFX11>, 1320 VOP3OpSel_gfx11<op, ps.Pfl>, 1321 MnemonicAlias<ps.Mnemonic, asmName>, Requires<[isGFX11Plus]>; 1322 foreach _ = BoolToList<!not(ps.Pfl.HasOpSel)>.ret in 1323 def _e64_gfx11 : 1324 VOP3_Real<ps, SIEncodingFamily.GFX11>, 1325 VOP3e_gfx11<op, ps.Pfl>, 1326 MnemonicAlias<ps.Mnemonic, asmName>, Requires<[isGFX11Plus]>; 1327 } 1328 } 1329 // for READLANE/WRITELANE 1330 multiclass VOP3_Real_No_Suffix_gfx11<bits<10> op, string opName = NAME> { 1331 defvar ps = !cast<VOP_Pseudo>(opName); 1332 def _e64_gfx11 : 1333 VOP3_Real<ps, SIEncodingFamily.GFX11>, 1334 VOP3e_gfx11<op, ps.Pfl>; 1335 } 1336 multiclass VOP3_Real_dpp_Base_gfx11<bits<10> op, string opName = NAME> { 1337 def _e64_dpp_gfx11 : VOP3_DPP16<op, !cast<VOP_DPP_Pseudo>(opName#"_e64"#"_dpp"), SIEncodingFamily.GFX11> { 1338 let DecoderNamespace = "DPPGFX11"; 1339 } 1340 } 1341 multiclass VOP3_Real_dpp_with_name_gfx11<bits<10> op, string opName, 1342 string asmName> { 1343 defvar ps = !cast<VOP3_Pseudo>(opName#"_e64"); 1344 let AsmString = asmName # ps.Pfl.AsmVOP3DPP16, DecoderNamespace = "DPPGFX11" in { 1345 defm NAME : VOP3_Real_dpp_Base_gfx11<op, opName>; 1346 } 1347 } 1348 multiclass VOP3_Real_dpp8_Base_gfx11<bits<10> op, string opName = NAME> { 1349 defvar ps = !cast<VOP3_Pseudo>(opName#"_e64"); 1350 def _e64_dpp8_gfx11 : Base_VOP3_DPP8<op, ps> { 1351 let DecoderNamespace = "DPP8GFX11"; 1352 } 1353 } 1354 multiclass VOP3_Real_dpp8_with_name_gfx11<bits<10> op, string opName, 1355 string asmName> { 1356 defvar ps = !cast<VOP3_Pseudo>(opName#"_e64"); 1357 let AsmString = asmName # ps.Pfl.AsmVOP3DPP8, DecoderNamespace = "DPP8GFX11" in { 1358 defm NAME : VOP3_Real_dpp8_Base_gfx11<op, opName>; 1359 } 1360 } 1361 multiclass VOP3be_Real_gfx11<bits<10> op, string opName, string asmName, 1362 bit isSingle = 0> { 1363 defvar ps = !cast<VOP3_Pseudo>(opName#"_e64"); 1364 let IsSingle = !or(isSingle, ps.Pfl.IsSingle) in 1365 def _e64_gfx11 : 1366 VOP3_Real<ps, SIEncodingFamily.GFX11, asmName>, 1367 VOP3be_gfx11<op, ps.Pfl> ; 1368 } 1369 multiclass VOP3be_Real_dpp_gfx11<bits<10> op, string opName, string asmName> { 1370 defvar ps = !cast<VOP3_Pseudo>(opName #"_e64"); 1371 defvar dpp_ps = !cast<VOP_DPP_Pseudo>(opName #"_e64" #"_dpp"); 1372 def _e64_dpp_gfx11 : Base_VOP3b_DPP16<op, dpp_ps, asmName>, 1373 SIMCInstr<dpp_ps.PseudoInstr, SIEncodingFamily.GFX11> { 1374 let DecoderNamespace = "DPPGFX11"; 1375 } 1376 } 1377 multiclass VOP3be_Real_dpp8_gfx11<bits<10> op, string opName, string asmName> { 1378 defvar ps = !cast<VOP3_Pseudo>(opName #"_e64"); 1379 def _e64_dpp8_gfx11 : VOP3b_DPP8_Base<op, ps, asmName> { 1380 let DecoderNamespace = "DPP8GFX11"; 1381 } 1382 } 1383} // End AssemblerPredicate = isGFX11Only, DecoderNamespace = "GFX11" 1384 1385// VOP1 and VOP2 depend on these triple defs 1386multiclass VOP3_Realtriple_gfx11<bits<10> op, 1387 bit isSingle = 0, string opName = NAME> : 1388 VOP3_Real_Base_gfx11<op, opName, isSingle>, 1389 VOP3_Real_dpp_Base_gfx11<op, opName>, 1390 VOP3_Real_dpp8_Base_gfx11<op, opName>; 1391 1392multiclass VOP3Only_Realtriple_gfx11<bits<10> op> : 1393 VOP3_Realtriple_gfx11<op, 1>; 1394 1395multiclass VOP3_Realtriple_with_name_gfx11<bits<10> op, string opName, 1396 string asmName, bit isSingle = 0> : 1397 VOP3_Real_with_name_gfx11<op, opName, asmName, isSingle>, 1398 VOP3_Real_dpp_with_name_gfx11<op, opName, asmName>, 1399 VOP3_Real_dpp8_with_name_gfx11<op, opName, asmName>; 1400 1401multiclass VOP3Only_Realtriple_with_name_gfx11<bits<10> op, string opName, 1402 string asmName> : 1403 VOP3_Realtriple_with_name_gfx11<op, opName, asmName, 1>; 1404 1405multiclass VOP3be_Realtriple_gfx11< 1406 bits<10> op, bit isSingle = 0, string opName = NAME, 1407 string asmName = !cast<VOP_Pseudo>(opName#"_e64").Mnemonic> : 1408 VOP3be_Real_gfx11<op, opName, asmName, isSingle>, 1409 VOP3be_Real_dpp_gfx11<op, opName, asmName>, 1410 VOP3be_Real_dpp8_gfx11<op, opName, asmName>; 1411 1412multiclass VOP3beOnly_Realtriple_gfx11<bits<10> op> : 1413 VOP3be_Realtriple_gfx11<op, 1>; 1414 1415include "VOPCInstructions.td" 1416include "VOP1Instructions.td" 1417include "VOP2Instructions.td" 1418include "VOP3Instructions.td" 1419include "VOP3PInstructions.td" 1420 1421 1422class VOPInfoTable <string Format> : GenericTable { 1423 let FilterClass = Format # "_Real"; 1424 let CppTypeName = "VOPInfo"; 1425 let Fields = ["Opcode", "IsSingle"]; 1426 1427 let PrimaryKey = ["Opcode"]; 1428 let PrimaryKeyName = "get" # Format # "OpcodeHelper"; 1429} 1430 1431def VOP1InfoTable : VOPInfoTable<"VOP1">; 1432def VOP2InfoTable : VOPInfoTable<"VOP2">; 1433def VOP3InfoTable : VOPInfoTable<"VOP3">; 1434