1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx1013 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,GFX1013 %s
3; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,GFX1030 %s
4; RUN: not --crash llc -march=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERR %s
5; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX11 %s
6
7; uint4 llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(uint node_ptr, float ray_extent, float3 ray_origin, float3 ray_dir, float3 ray_inv_dir, uint4 texture_descr)
8; uint4 llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(uint node_ptr, float ray_extent, float3 ray_origin, half3 ray_dir, half3 ray_inv_dir, uint4 texture_descr)
9; uint4 llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(ulong node_ptr, float ray_extent, float3 ray_origin, float3 ray_dir, float3 ray_inv_dir, uint4 texture_descr)
10; uint4 llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(ulong node_ptr, float ray_extent, float3 ray_origin, half3 ray_dir, half3 ray_inv_dir, uint4 texture_descr)
11
12declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32, float, <3 x float>, <3 x float>, <3 x float>, <4 x i32>)
13declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32, float, <3 x float>, <3 x half>, <3 x half>, <4 x i32>)
14declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64, float, <3 x float>, <3 x float>, <3 x float>, <4 x i32>)
15declare <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64, float, <3 x float>, <3 x half>, <3 x half>, <4 x i32>)
16
17; ERR: in function image_bvh_intersect_ray{{.*}}intrinsic not supported on subtarget
18; Arguments are flattened to represent the actual VGPR_A layout, so we have no
19; extra moves in the generated kernel.
20define amdgpu_ps <4 x float> @image_bvh_intersect_ray(i32 %node_ptr, float %ray_extent, float %ray_origin_x, float %ray_origin_y, float %ray_origin_z, float %ray_dir_x, float %ray_dir_y, float %ray_dir_z, float %ray_inv_dir_x, float %ray_inv_dir_y, float %ray_inv_dir_z, <4 x i32> inreg %tdescr) {
21; GCN-LABEL: image_bvh_intersect_ray:
22; GCN:       ; %bb.0: ; %main_body
23; GCN-NEXT:    image_bvh_intersect_ray v[0:3], v[0:15], s[0:3]
24; GCN-NEXT:    s_waitcnt vmcnt(0)
25; GCN-NEXT:    ; return to shader part epilog
26main_body:
27  %ray_origin0 = insertelement <3 x float> undef, float %ray_origin_x, i32 0
28  %ray_origin1 = insertelement <3 x float> %ray_origin0, float %ray_origin_y, i32 1
29  %ray_origin = insertelement <3 x float> %ray_origin1, float %ray_origin_z, i32 2
30  %ray_dir0 = insertelement <3 x float> undef, float %ray_dir_x, i32 0
31  %ray_dir1 = insertelement <3 x float> %ray_dir0, float %ray_dir_y, i32 1
32  %ray_dir = insertelement <3 x float> %ray_dir1, float %ray_dir_z, i32 2
33  %ray_inv_dir0 = insertelement <3 x float> undef, float %ray_inv_dir_x, i32 0
34  %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float %ray_inv_dir_y, i32 1
35  %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float %ray_inv_dir_z, i32 2
36  %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
37 %r = bitcast <4 x i32> %v to <4 x float>
38 ret <4 x float> %r
39}
40
41define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16(i32 inreg %node_ptr, float inreg %ray_extent, <3 x float> inreg %ray_origin, <3 x half> inreg %ray_dir, <3 x half> inreg %ray_inv_dir, <4 x i32> inreg %tdescr) {
42; GFX10-LABEL: image_bvh_intersect_ray_a16:
43; GFX10:       ; %bb.0: ; %main_body
44; GFX10-NEXT:    s_mov_b32 s15, s12
45; GFX10-NEXT:    s_mov_b32 s12, s9
46; GFX10-NEXT:    s_lshr_b32 s9, s7, 16
47; GFX10-NEXT:    s_pack_ll_b32_b16 s6, s6, s7
48; GFX10-NEXT:    s_pack_ll_b32_b16 s7, s9, s8
49; GFX10-NEXT:    v_mov_b32_e32 v0, s0
50; GFX10-NEXT:    v_mov_b32_e32 v1, s1
51; GFX10-NEXT:    v_mov_b32_e32 v2, s2
52; GFX10-NEXT:    v_mov_b32_e32 v3, s3
53; GFX10-NEXT:    v_mov_b32_e32 v4, s4
54; GFX10-NEXT:    v_mov_b32_e32 v5, s5
55; GFX10-NEXT:    v_mov_b32_e32 v6, s6
56; GFX10-NEXT:    v_mov_b32_e32 v7, s7
57; GFX10-NEXT:    s_mov_b32 s14, s11
58; GFX10-NEXT:    s_mov_b32 s13, s10
59; GFX10-NEXT:    image_bvh_intersect_ray v[0:3], v[0:7], s[12:15] a16
60; GFX10-NEXT:    s_waitcnt vmcnt(0)
61; GFX10-NEXT:    ; return to shader part epilog
62;
63; GFX11-LABEL: image_bvh_intersect_ray_a16:
64; GFX11:       ; %bb.0: ; %main_body
65; GFX11-NEXT:    v_mov_b32_e32 v0, s2
66; GFX11-NEXT:    v_mov_b32_e32 v1, s3
67; GFX11-NEXT:    s_lshr_b32 s2, s7, 16
68; GFX11-NEXT:    s_lshr_b32 s3, s5, 16
69; GFX11-NEXT:    v_mov_b32_e32 v2, s4
70; GFX11-NEXT:    s_pack_ll_b32_b16 s2, s3, s2
71; GFX11-NEXT:    s_pack_ll_b32_b16 s3, s5, s7
72; GFX11-NEXT:    s_pack_ll_b32_b16 s4, s6, s8
73; GFX11-NEXT:    v_mov_b32_e32 v3, s3
74; GFX11-NEXT:    v_mov_b32_e32 v4, s2
75; GFX11-NEXT:    v_mov_b32_e32 v5, s4
76; GFX11-NEXT:    v_mov_b32_e32 v6, s0
77; GFX11-NEXT:    v_mov_b32_e32 v7, s1
78; GFX11-NEXT:    s_mov_b32 s15, s12
79; GFX11-NEXT:    s_mov_b32 s14, s11
80; GFX11-NEXT:    s_mov_b32 s13, s10
81; GFX11-NEXT:    s_mov_b32 s12, s9
82; GFX11-NEXT:    image_bvh_intersect_ray v[0:3], [v6, v7, v[0:2], v[3:5]], s[12:15] a16
83; GFX11-NEXT:    s_waitcnt vmcnt(0)
84; GFX11-NEXT:    ; return to shader part epilog
85main_body:
86  %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
87  %r = bitcast <4 x i32> %v to <4 x float>
88  ret <4 x float> %r
89}
90
91; Arguments are flattened to represent the actual VGPR_A layout, so we have no
92; extra moves in the generated kernel.
93define amdgpu_ps <4 x float> @image_bvh64_intersect_ray(<2 x i32> %node_ptr_vec, float %ray_extent, float %ray_origin_x, float %ray_origin_y, float %ray_origin_z, float %ray_dir_x, float %ray_dir_y, float %ray_dir_z, float %ray_inv_dir_x, float %ray_inv_dir_y, float %ray_inv_dir_z, <4 x i32> inreg %tdescr) {
94; GCN-LABEL: image_bvh64_intersect_ray:
95; GCN:       ; %bb.0: ; %main_body
96; GCN-NEXT:    image_bvh64_intersect_ray v[0:3], v[0:15], s[0:3]
97; GCN-NEXT:    s_waitcnt vmcnt(0)
98; GCN-NEXT:    ; return to shader part epilog
99main_body:
100  %node_ptr = bitcast <2 x i32> %node_ptr_vec to i64
101  %ray_origin0 = insertelement <3 x float> undef, float %ray_origin_x, i32 0
102  %ray_origin1 = insertelement <3 x float> %ray_origin0, float %ray_origin_y, i32 1
103  %ray_origin = insertelement <3 x float> %ray_origin1, float %ray_origin_z, i32 2
104  %ray_dir0 = insertelement <3 x float> undef, float %ray_dir_x, i32 0
105  %ray_dir1 = insertelement <3 x float> %ray_dir0, float %ray_dir_y, i32 1
106  %ray_dir = insertelement <3 x float> %ray_dir1, float %ray_dir_z, i32 2
107  %ray_inv_dir0 = insertelement <3 x float> undef, float %ray_inv_dir_x, i32 0
108  %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float %ray_inv_dir_y, i32 1
109  %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float %ray_inv_dir_z, i32 2
110  %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
111 %r = bitcast <4 x i32> %v to <4 x float>
112 ret <4 x float> %r
113}
114
115define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16(i64 inreg %node_ptr, float inreg %ray_extent, <3 x float> inreg %ray_origin, <3 x half> inreg %ray_dir, <3 x half> inreg %ray_inv_dir, <4 x i32> inreg %tdescr) {
116; GFX10-LABEL: image_bvh64_intersect_ray_a16:
117; GFX10:       ; %bb.0: ; %main_body
118; GFX10-NEXT:    s_mov_b32 s14, s12
119; GFX10-NEXT:    s_mov_b32 s12, s10
120; GFX10-NEXT:    s_lshr_b32 s10, s8, 16
121; GFX10-NEXT:    s_pack_ll_b32_b16 s7, s7, s8
122; GFX10-NEXT:    s_pack_ll_b32_b16 s8, s10, s9
123; GFX10-NEXT:    v_mov_b32_e32 v0, s0
124; GFX10-NEXT:    v_mov_b32_e32 v1, s1
125; GFX10-NEXT:    v_mov_b32_e32 v2, s2
126; GFX10-NEXT:    v_mov_b32_e32 v3, s3
127; GFX10-NEXT:    v_mov_b32_e32 v4, s4
128; GFX10-NEXT:    v_mov_b32_e32 v5, s5
129; GFX10-NEXT:    v_mov_b32_e32 v6, s6
130; GFX10-NEXT:    v_mov_b32_e32 v7, s7
131; GFX10-NEXT:    v_mov_b32_e32 v8, s8
132; GFX10-NEXT:    s_mov_b32 s15, s13
133; GFX10-NEXT:    s_mov_b32 s13, s11
134; GFX10-NEXT:    image_bvh64_intersect_ray v[0:3], v[0:15], s[12:15] a16
135; GFX10-NEXT:    s_waitcnt vmcnt(0)
136; GFX10-NEXT:    ; return to shader part epilog
137;
138; GFX11-LABEL: image_bvh64_intersect_ray_a16:
139; GFX11:       ; %bb.0: ; %main_body
140; GFX11-NEXT:    v_mov_b32_e32 v0, s3
141; GFX11-NEXT:    v_mov_b32_e32 v6, s0
142; GFX11-NEXT:    s_lshr_b32 s0, s8, 16
143; GFX11-NEXT:    s_lshr_b32 s3, s6, 16
144; GFX11-NEXT:    v_mov_b32_e32 v7, s1
145; GFX11-NEXT:    s_pack_ll_b32_b16 s0, s3, s0
146; GFX11-NEXT:    s_pack_ll_b32_b16 s1, s6, s8
147; GFX11-NEXT:    s_pack_ll_b32_b16 s3, s7, s9
148; GFX11-NEXT:    v_mov_b32_e32 v1, s4
149; GFX11-NEXT:    v_mov_b32_e32 v2, s5
150; GFX11-NEXT:    v_mov_b32_e32 v3, s1
151; GFX11-NEXT:    v_mov_b32_e32 v4, s0
152; GFX11-NEXT:    v_mov_b32_e32 v5, s3
153; GFX11-NEXT:    v_mov_b32_e32 v8, s2
154; GFX11-NEXT:    s_mov_b32 s15, s13
155; GFX11-NEXT:    s_mov_b32 s14, s12
156; GFX11-NEXT:    s_mov_b32 s13, s11
157; GFX11-NEXT:    s_mov_b32 s12, s10
158; GFX11-NEXT:    image_bvh64_intersect_ray v[0:3], [v[6:7], v8, v[0:2], v[3:5]], s[12:15] a16
159; GFX11-NEXT:    s_waitcnt vmcnt(0)
160; GFX11-NEXT:    ; return to shader part epilog
161main_body:
162  %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
163  %r = bitcast <4 x i32> %v to <4 x float>
164  ret <4 x float> %r
165}
166
167; TODO: NSA reassign is very limited and cannot work with VGPR tuples and subregs.
168
169define amdgpu_kernel void @image_bvh_intersect_ray_nsa_reassign(i32* %p_node_ptr, float* %p_ray, <4 x i32> inreg %tdescr) {
170; GFX1013-LABEL: image_bvh_intersect_ray_nsa_reassign:
171; GFX1013:       ; %bb.0: ; %main_body
172; GFX1013-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
173; GFX1013-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
174; GFX1013-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
175; GFX1013-NEXT:    v_mov_b32_e32 v6, 4.0
176; GFX1013-NEXT:    v_mov_b32_e32 v7, 0x40a00000
177; GFX1013-NEXT:    v_mov_b32_e32 v8, 0x40c00000
178; GFX1013-NEXT:    v_mov_b32_e32 v9, 0x40e00000
179; GFX1013-NEXT:    v_mov_b32_e32 v10, 0x41000000
180; GFX1013-NEXT:    s_waitcnt lgkmcnt(0)
181; GFX1013-NEXT:    v_add_co_u32 v2, s4, s4, v0
182; GFX1013-NEXT:    v_add_co_ci_u32_e64 v3, s4, s5, 0, s4
183; GFX1013-NEXT:    v_add_co_u32 v4, s4, s6, v0
184; GFX1013-NEXT:    v_add_co_ci_u32_e64 v5, s4, s7, 0, s4
185; GFX1013-NEXT:    flat_load_dword v0, v[2:3]
186; GFX1013-NEXT:    flat_load_dword v1, v[4:5]
187; GFX1013-NEXT:    v_mov_b32_e32 v2, 0
188; GFX1013-NEXT:    v_mov_b32_e32 v3, 1.0
189; GFX1013-NEXT:    v_mov_b32_e32 v4, 2.0
190; GFX1013-NEXT:    v_mov_b32_e32 v5, 0x40400000
191; GFX1013-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
192; GFX1013-NEXT:    image_bvh_intersect_ray v[0:3], v[0:15], s[0:3]
193; GFX1013-NEXT:    s_waitcnt vmcnt(0)
194; GFX1013-NEXT:    flat_store_dwordx4 v[0:1], v[0:3]
195; GFX1013-NEXT:    s_endpgm
196;
197; GFX1030-LABEL: image_bvh_intersect_ray_nsa_reassign:
198; GFX1030:       ; %bb.0: ; %main_body
199; GFX1030-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
200; GFX1030-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
201; GFX1030-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
202; GFX1030-NEXT:    v_mov_b32_e32 v10, 0x41000000
203; GFX1030-NEXT:    v_mov_b32_e32 v9, 0x40e00000
204; GFX1030-NEXT:    v_mov_b32_e32 v8, 0x40c00000
205; GFX1030-NEXT:    v_mov_b32_e32 v7, 0x40a00000
206; GFX1030-NEXT:    v_mov_b32_e32 v6, 4.0
207; GFX1030-NEXT:    v_mov_b32_e32 v5, 0x40400000
208; GFX1030-NEXT:    v_mov_b32_e32 v4, 2.0
209; GFX1030-NEXT:    s_waitcnt lgkmcnt(0)
210; GFX1030-NEXT:    v_add_co_u32 v0, s4, s4, v2
211; GFX1030-NEXT:    v_add_co_ci_u32_e64 v1, null, s5, 0, s4
212; GFX1030-NEXT:    v_add_co_u32 v2, s4, s6, v2
213; GFX1030-NEXT:    v_add_co_ci_u32_e64 v3, null, s7, 0, s4
214; GFX1030-NEXT:    flat_load_dword v0, v[0:1]
215; GFX1030-NEXT:    flat_load_dword v1, v[2:3]
216; GFX1030-NEXT:    v_mov_b32_e32 v2, 0
217; GFX1030-NEXT:    v_mov_b32_e32 v3, 1.0
218; GFX1030-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
219; GFX1030-NEXT:    image_bvh_intersect_ray v[0:3], v[0:15], s[0:3]
220; GFX1030-NEXT:    s_waitcnt vmcnt(0)
221; GFX1030-NEXT:    flat_store_dwordx4 v[0:1], v[0:3]
222; GFX1030-NEXT:    s_endpgm
223;
224; GFX11-LABEL: image_bvh_intersect_ray_nsa_reassign:
225; GFX11:       ; %bb.0: ; %main_body
226; GFX11-NEXT:    s_load_b128 s[4:7], s[0:1], 0x24
227; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
228; GFX11-NEXT:    s_load_b128 s[0:3], s[0:1], 0x34
229; GFX11-NEXT:    v_mov_b32_e32 v4, 4.0
230; GFX11-NEXT:    v_mov_b32_e32 v5, 0x40a00000
231; GFX11-NEXT:    v_mov_b32_e32 v6, 0
232; GFX11-NEXT:    v_mov_b32_e32 v7, 1.0
233; GFX11-NEXT:    v_mov_b32_e32 v8, 2.0
234; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
235; GFX11-NEXT:    v_add_co_u32 v0, s4, s4, v2
236; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
237; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, s5, 0, s4
238; GFX11-NEXT:    v_add_co_u32 v2, s4, s6, v2
239; GFX11-NEXT:    v_add_co_ci_u32_e64 v3, null, s7, 0, s4
240; GFX11-NEXT:    flat_load_b32 v9, v[0:1]
241; GFX11-NEXT:    flat_load_b32 v10, v[2:3]
242; GFX11-NEXT:    v_mov_b32_e32 v0, 0x40c00000
243; GFX11-NEXT:    v_mov_b32_e32 v1, 0x40e00000
244; GFX11-NEXT:    v_mov_b32_e32 v2, 0x41000000
245; GFX11-NEXT:    v_mov_b32_e32 v3, 0x40400000
246; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
247; GFX11-NEXT:    image_bvh_intersect_ray v[0:3], [v9, v10, v[6:8], v[3:5], v[0:2]], s[0:3]
248; GFX11-NEXT:    s_waitcnt vmcnt(0)
249; GFX11-NEXT:    flat_store_b128 v[0:1], v[0:3]
250; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
251; GFX11-NEXT:    s_endpgm
252main_body:
253  %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
254  %gep_node_ptr = getelementptr inbounds i32, i32* %p_node_ptr, i32 %lid
255  %node_ptr = load i32, i32* %gep_node_ptr, align 4
256  %gep_ray = getelementptr inbounds float, float* %p_ray, i32 %lid
257  %ray_extent = load float, float* %gep_ray, align 4
258  %ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
259  %ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
260  %ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
261  %ray_dir0 = insertelement <3 x float> undef, float 3.0, i32 0
262  %ray_dir1 = insertelement <3 x float> %ray_dir0, float 4.0, i32 1
263  %ray_dir = insertelement <3 x float> %ray_dir1, float 5.0, i32 2
264  %ray_inv_dir0 = insertelement <3 x float> undef, float 6.0, i32 0
265  %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float 7.0, i32 1
266  %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float 8.0, i32 2
267  %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
268  store <4 x i32> %v, <4 x i32>* undef
269  ret void
270}
271
272define amdgpu_kernel void @image_bvh_intersect_ray_a16_nsa_reassign(i32* %p_node_ptr, float* %p_ray, <4 x i32> inreg %tdescr) {
273; GFX1013-LABEL: image_bvh_intersect_ray_a16_nsa_reassign:
274; GFX1013:       ; %bb.0: ; %main_body
275; GFX1013-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
276; GFX1013-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
277; GFX1013-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
278; GFX1013-NEXT:    v_mov_b32_e32 v6, 0x46004500
279; GFX1013-NEXT:    v_mov_b32_e32 v7, 0x48004700
280; GFX1013-NEXT:    s_waitcnt lgkmcnt(0)
281; GFX1013-NEXT:    v_add_co_u32 v2, s4, s4, v0
282; GFX1013-NEXT:    v_add_co_ci_u32_e64 v3, s4, s5, 0, s4
283; GFX1013-NEXT:    v_add_co_u32 v4, s4, s6, v0
284; GFX1013-NEXT:    v_add_co_ci_u32_e64 v5, s4, s7, 0, s4
285; GFX1013-NEXT:    flat_load_dword v0, v[2:3]
286; GFX1013-NEXT:    flat_load_dword v1, v[4:5]
287; GFX1013-NEXT:    v_mov_b32_e32 v2, 0
288; GFX1013-NEXT:    v_mov_b32_e32 v3, 1.0
289; GFX1013-NEXT:    v_mov_b32_e32 v4, 2.0
290; GFX1013-NEXT:    v_mov_b32_e32 v5, 0x44004200
291; GFX1013-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
292; GFX1013-NEXT:    image_bvh_intersect_ray v[0:3], v[0:7], s[0:3] a16
293; GFX1013-NEXT:    s_waitcnt vmcnt(0)
294; GFX1013-NEXT:    flat_store_dwordx4 v[0:1], v[0:3]
295; GFX1013-NEXT:    s_endpgm
296;
297; GFX1030-LABEL: image_bvh_intersect_ray_a16_nsa_reassign:
298; GFX1030:       ; %bb.0: ; %main_body
299; GFX1030-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
300; GFX1030-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
301; GFX1030-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
302; GFX1030-NEXT:    v_mov_b32_e32 v4, 2.0
303; GFX1030-NEXT:    v_mov_b32_e32 v5, 0x44004200
304; GFX1030-NEXT:    v_mov_b32_e32 v6, 0x46004500
305; GFX1030-NEXT:    v_mov_b32_e32 v7, 0x48004700
306; GFX1030-NEXT:    s_waitcnt lgkmcnt(0)
307; GFX1030-NEXT:    v_add_co_u32 v0, s4, s4, v2
308; GFX1030-NEXT:    v_add_co_ci_u32_e64 v1, null, s5, 0, s4
309; GFX1030-NEXT:    v_add_co_u32 v2, s4, s6, v2
310; GFX1030-NEXT:    v_add_co_ci_u32_e64 v3, null, s7, 0, s4
311; GFX1030-NEXT:    flat_load_dword v0, v[0:1]
312; GFX1030-NEXT:    flat_load_dword v1, v[2:3]
313; GFX1030-NEXT:    v_mov_b32_e32 v2, 0
314; GFX1030-NEXT:    v_mov_b32_e32 v3, 1.0
315; GFX1030-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
316; GFX1030-NEXT:    image_bvh_intersect_ray v[0:3], v[0:7], s[0:3] a16
317; GFX1030-NEXT:    s_waitcnt vmcnt(0)
318; GFX1030-NEXT:    flat_store_dwordx4 v[0:1], v[0:3]
319; GFX1030-NEXT:    s_endpgm
320;
321; GFX11-LABEL: image_bvh_intersect_ray_a16_nsa_reassign:
322; GFX11:       ; %bb.0: ; %main_body
323; GFX11-NEXT:    s_load_b128 s[4:7], s[0:1], 0x24
324; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
325; GFX11-NEXT:    s_load_b128 s[0:3], s[0:1], 0x34
326; GFX11-NEXT:    v_mov_b32_e32 v4, 1.0
327; GFX11-NEXT:    v_mov_b32_e32 v5, 2.0
328; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
329; GFX11-NEXT:    v_add_co_u32 v0, s4, s4, v2
330; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
331; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, s5, 0, s4
332; GFX11-NEXT:    v_add_co_u32 v2, s4, s6, v2
333; GFX11-NEXT:    v_add_co_ci_u32_e64 v3, null, s7, 0, s4
334; GFX11-NEXT:    flat_load_b32 v6, v[0:1]
335; GFX11-NEXT:    flat_load_b32 v7, v[2:3]
336; GFX11-NEXT:    v_mov_b32_e32 v0, 0x46004200
337; GFX11-NEXT:    v_mov_b32_e32 v1, 0x47004400
338; GFX11-NEXT:    v_mov_b32_e32 v2, 0x48004500
339; GFX11-NEXT:    v_mov_b32_e32 v3, 0
340; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
341; GFX11-NEXT:    image_bvh_intersect_ray v[0:3], [v6, v7, v[3:5], v[0:2]], s[0:3] a16
342; GFX11-NEXT:    s_waitcnt vmcnt(0)
343; GFX11-NEXT:    flat_store_b128 v[0:1], v[0:3]
344; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
345; GFX11-NEXT:    s_endpgm
346main_body:
347  %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
348  %gep_node_ptr = getelementptr inbounds i32, i32* %p_node_ptr, i32 %lid
349  %node_ptr = load i32, i32* %gep_node_ptr, align 4
350  %gep_ray = getelementptr inbounds float, float* %p_ray, i32 %lid
351  %ray_extent = load float, float* %gep_ray, align 4
352  %ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
353  %ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
354  %ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
355  %ray_dir0 = insertelement <3 x half> undef, half 3.0, i32 0
356  %ray_dir1 = insertelement <3 x half> %ray_dir0, half 4.0, i32 1
357  %ray_dir = insertelement <3 x half> %ray_dir1, half 5.0, i32 2
358  %ray_inv_dir0 = insertelement <3 x half> undef, half 6.0, i32 0
359  %ray_inv_dir1 = insertelement <3 x half> %ray_inv_dir0, half 7.0, i32 1
360  %ray_inv_dir = insertelement <3 x half> %ray_inv_dir1, half 8.0, i32 2
361  %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
362  store <4 x i32> %v, <4 x i32>* undef
363  ret void
364}
365
366define amdgpu_kernel void @image_bvh64_intersect_ray_nsa_reassign(float* %p_ray, <4 x i32> inreg %tdescr) {
367; GFX1013-LABEL: image_bvh64_intersect_ray_nsa_reassign:
368; GFX1013:       ; %bb.0: ; %main_body
369; GFX1013-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
370; GFX1013-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
371; GFX1013-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
372; GFX1013-NEXT:    v_mov_b32_e32 v3, 0
373; GFX1013-NEXT:    v_mov_b32_e32 v4, 1.0
374; GFX1013-NEXT:    v_mov_b32_e32 v5, 2.0
375; GFX1013-NEXT:    v_mov_b32_e32 v6, 0x40400000
376; GFX1013-NEXT:    v_mov_b32_e32 v7, 4.0
377; GFX1013-NEXT:    v_mov_b32_e32 v8, 0x40a00000
378; GFX1013-NEXT:    v_mov_b32_e32 v9, 0x40c00000
379; GFX1013-NEXT:    v_mov_b32_e32 v10, 0x40e00000
380; GFX1013-NEXT:    v_mov_b32_e32 v11, 0x41000000
381; GFX1013-NEXT:    s_waitcnt lgkmcnt(0)
382; GFX1013-NEXT:    v_add_co_u32 v0, s4, s4, v0
383; GFX1013-NEXT:    v_add_co_ci_u32_e64 v1, s4, s5, 0, s4
384; GFX1013-NEXT:    flat_load_dword v2, v[0:1]
385; GFX1013-NEXT:    v_mov_b32_e32 v0, 0xb36211c7
386; GFX1013-NEXT:    v_mov_b32_e32 v1, 0x102
387; GFX1013-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
388; GFX1013-NEXT:    image_bvh64_intersect_ray v[0:3], v[0:15], s[0:3]
389; GFX1013-NEXT:    s_waitcnt vmcnt(0)
390; GFX1013-NEXT:    flat_store_dwordx4 v[0:1], v[0:3]
391; GFX1013-NEXT:    s_endpgm
392;
393; GFX1030-LABEL: image_bvh64_intersect_ray_nsa_reassign:
394; GFX1030:       ; %bb.0: ; %main_body
395; GFX1030-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
396; GFX1030-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
397; GFX1030-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
398; GFX1030-NEXT:    v_mov_b32_e32 v3, 0
399; GFX1030-NEXT:    v_mov_b32_e32 v11, 0x41000000
400; GFX1030-NEXT:    v_mov_b32_e32 v10, 0x40e00000
401; GFX1030-NEXT:    v_mov_b32_e32 v9, 0x40c00000
402; GFX1030-NEXT:    v_mov_b32_e32 v8, 0x40a00000
403; GFX1030-NEXT:    v_mov_b32_e32 v7, 4.0
404; GFX1030-NEXT:    v_mov_b32_e32 v6, 0x40400000
405; GFX1030-NEXT:    v_mov_b32_e32 v5, 2.0
406; GFX1030-NEXT:    v_mov_b32_e32 v4, 1.0
407; GFX1030-NEXT:    s_waitcnt lgkmcnt(0)
408; GFX1030-NEXT:    v_add_co_u32 v0, s4, s4, v0
409; GFX1030-NEXT:    v_add_co_ci_u32_e64 v1, null, s5, 0, s4
410; GFX1030-NEXT:    flat_load_dword v2, v[0:1]
411; GFX1030-NEXT:    v_mov_b32_e32 v1, 0x102
412; GFX1030-NEXT:    v_mov_b32_e32 v0, 0xb36211c7
413; GFX1030-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
414; GFX1030-NEXT:    image_bvh64_intersect_ray v[0:3], v[0:15], s[0:3]
415; GFX1030-NEXT:    s_waitcnt vmcnt(0)
416; GFX1030-NEXT:    flat_store_dwordx4 v[0:1], v[0:3]
417; GFX1030-NEXT:    s_endpgm
418;
419; GFX11-LABEL: image_bvh64_intersect_ray_nsa_reassign:
420; GFX11:       ; %bb.0: ; %main_body
421; GFX11-NEXT:    s_load_b64 s[4:5], s[0:1], 0x24
422; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
423; GFX11-NEXT:    s_load_b128 s[0:3], s[0:1], 0x34
424; GFX11-NEXT:    v_mov_b32_e32 v2, 0x41000000
425; GFX11-NEXT:    v_mov_b32_e32 v3, 0x40400000
426; GFX11-NEXT:    v_mov_b32_e32 v4, 4.0
427; GFX11-NEXT:    v_mov_b32_e32 v5, 0x40a00000
428; GFX11-NEXT:    v_mov_b32_e32 v6, 0
429; GFX11-NEXT:    v_mov_b32_e32 v7, 1.0
430; GFX11-NEXT:    v_mov_b32_e32 v8, 2.0
431; GFX11-NEXT:    v_mov_b32_e32 v9, 0xb36211c7
432; GFX11-NEXT:    v_mov_b32_e32 v10, 0x102
433; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
434; GFX11-NEXT:    v_add_co_u32 v0, s4, s4, v0
435; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
436; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, s5, 0, s4
437; GFX11-NEXT:    flat_load_b32 v11, v[0:1]
438; GFX11-NEXT:    v_mov_b32_e32 v0, 0x40c00000
439; GFX11-NEXT:    v_mov_b32_e32 v1, 0x40e00000
440; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
441; GFX11-NEXT:    image_bvh64_intersect_ray v[0:3], [v[9:10], v11, v[6:8], v[3:5], v[0:2]], s[0:3]
442; GFX11-NEXT:    s_waitcnt vmcnt(0)
443; GFX11-NEXT:    flat_store_b128 v[0:1], v[0:3]
444; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
445; GFX11-NEXT:    s_endpgm
446main_body:
447  %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
448  %gep_ray = getelementptr inbounds float, float* %p_ray, i32 %lid
449  %ray_extent = load float, float* %gep_ray, align 4
450  %ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
451  %ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
452  %ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
453  %ray_dir0 = insertelement <3 x float> undef, float 3.0, i32 0
454  %ray_dir1 = insertelement <3 x float> %ray_dir0, float 4.0, i32 1
455  %ray_dir = insertelement <3 x float> %ray_dir1, float 5.0, i32 2
456  %ray_inv_dir0 = insertelement <3 x float> undef, float 6.0, i32 0
457  %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float 7.0, i32 1
458  %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float 8.0, i32 2
459  %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64 1111111111111, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
460  store <4 x i32> %v, <4 x i32>* undef
461  ret void
462}
463
464define amdgpu_kernel void @image_bvh64_intersect_ray_a16_nsa_reassign(float* %p_ray, <4 x i32> inreg %tdescr) {
465; GFX1013-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign:
466; GFX1013:       ; %bb.0: ; %main_body
467; GFX1013-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
468; GFX1013-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
469; GFX1013-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
470; GFX1013-NEXT:    v_mov_b32_e32 v3, 0
471; GFX1013-NEXT:    v_mov_b32_e32 v4, 1.0
472; GFX1013-NEXT:    v_mov_b32_e32 v5, 2.0
473; GFX1013-NEXT:    v_mov_b32_e32 v6, 0x44004200
474; GFX1013-NEXT:    v_mov_b32_e32 v7, 0x46004500
475; GFX1013-NEXT:    v_mov_b32_e32 v8, 0x48004700
476; GFX1013-NEXT:    s_waitcnt lgkmcnt(0)
477; GFX1013-NEXT:    v_add_co_u32 v0, s4, s4, v0
478; GFX1013-NEXT:    v_add_co_ci_u32_e64 v1, s4, s5, 0, s4
479; GFX1013-NEXT:    flat_load_dword v2, v[0:1]
480; GFX1013-NEXT:    v_mov_b32_e32 v0, 0xb36211c6
481; GFX1013-NEXT:    v_mov_b32_e32 v1, 0x102
482; GFX1013-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
483; GFX1013-NEXT:    image_bvh64_intersect_ray v[0:3], v[0:15], s[0:3] a16
484; GFX1013-NEXT:    s_waitcnt vmcnt(0)
485; GFX1013-NEXT:    flat_store_dwordx4 v[0:1], v[0:3]
486; GFX1013-NEXT:    s_endpgm
487;
488; GFX1030-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign:
489; GFX1030:       ; %bb.0: ; %main_body
490; GFX1030-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
491; GFX1030-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
492; GFX1030-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
493; GFX1030-NEXT:    v_mov_b32_e32 v3, 0
494; GFX1030-NEXT:    v_mov_b32_e32 v5, 2.0
495; GFX1030-NEXT:    v_mov_b32_e32 v4, 1.0
496; GFX1030-NEXT:    v_mov_b32_e32 v6, 0x44004200
497; GFX1030-NEXT:    v_mov_b32_e32 v7, 0x46004500
498; GFX1030-NEXT:    v_mov_b32_e32 v8, 0x48004700
499; GFX1030-NEXT:    s_waitcnt lgkmcnt(0)
500; GFX1030-NEXT:    v_add_co_u32 v0, s4, s4, v0
501; GFX1030-NEXT:    v_add_co_ci_u32_e64 v1, null, s5, 0, s4
502; GFX1030-NEXT:    flat_load_dword v2, v[0:1]
503; GFX1030-NEXT:    v_mov_b32_e32 v1, 0x102
504; GFX1030-NEXT:    v_mov_b32_e32 v0, 0xb36211c6
505; GFX1030-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
506; GFX1030-NEXT:    image_bvh64_intersect_ray v[0:3], v[0:15], s[0:3] a16
507; GFX1030-NEXT:    s_waitcnt vmcnt(0)
508; GFX1030-NEXT:    flat_store_dwordx4 v[0:1], v[0:3]
509; GFX1030-NEXT:    s_endpgm
510;
511; GFX11-LABEL: image_bvh64_intersect_ray_a16_nsa_reassign:
512; GFX11:       ; %bb.0: ; %main_body
513; GFX11-NEXT:    s_load_b64 s[4:5], s[0:1], 0x24
514; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
515; GFX11-NEXT:    s_load_b128 s[0:3], s[0:1], 0x34
516; GFX11-NEXT:    v_mov_b32_e32 v2, 0x48004500
517; GFX11-NEXT:    v_mov_b32_e32 v3, 0
518; GFX11-NEXT:    v_mov_b32_e32 v4, 1.0
519; GFX11-NEXT:    v_mov_b32_e32 v5, 2.0
520; GFX11-NEXT:    v_mov_b32_e32 v6, 0xb36211c6
521; GFX11-NEXT:    v_mov_b32_e32 v7, 0x102
522; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
523; GFX11-NEXT:    v_add_co_u32 v0, s4, s4, v0
524; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
525; GFX11-NEXT:    v_add_co_ci_u32_e64 v1, null, s5, 0, s4
526; GFX11-NEXT:    flat_load_b32 v8, v[0:1]
527; GFX11-NEXT:    v_mov_b32_e32 v0, 0x46004200
528; GFX11-NEXT:    v_mov_b32_e32 v1, 0x47004400
529; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
530; GFX11-NEXT:    image_bvh64_intersect_ray v[0:3], [v[6:7], v8, v[3:5], v[0:2]], s[0:3] a16
531; GFX11-NEXT:    s_waitcnt vmcnt(0)
532; GFX11-NEXT:    flat_store_b128 v[0:1], v[0:3]
533; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
534; GFX11-NEXT:    s_endpgm
535main_body:
536  %lid = tail call i32 @llvm.amdgcn.workitem.id.x()
537  %gep_ray = getelementptr inbounds float, float* %p_ray, i32 %lid
538  %ray_extent = load float, float* %gep_ray, align 4
539  %ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
540  %ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
541  %ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
542  %ray_dir0 = insertelement <3 x half> undef, half 3.0, i32 0
543  %ray_dir1 = insertelement <3 x half> %ray_dir0, half 4.0, i32 1
544  %ray_dir = insertelement <3 x half> %ray_dir1, half 5.0, i32 2
545  %ray_inv_dir0 = insertelement <3 x half> undef, half 6.0, i32 0
546  %ray_inv_dir1 = insertelement <3 x half> %ray_inv_dir0, half 7.0, i32 1
547  %ray_inv_dir = insertelement <3 x half> %ray_inv_dir1, half 8.0, i32 2
548  %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64 1111111111110, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
549  store <4 x i32> %v, <4 x i32>* undef
550  ret void
551}
552
553declare i32 @llvm.amdgcn.workitem.id.x()
554