1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-xnack -verify-machineinstrs -debug-only=machine-scheduler < %s 2> %t | FileCheck --enable-var-scope --check-prefix=GFX9 %s
3; RUN: FileCheck --enable-var-scope --check-prefix=DBG %s < %t
4; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -debug-only=machine-scheduler < %s 2> %t | FileCheck --enable-var-scope --check-prefix=GFX10 %s
5; RUN: FileCheck --enable-var-scope --check-prefix=DBG %s < %t
6; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs -debug-only=machine-scheduler < %s 2> %t | FileCheck --enable-var-scope --check-prefix=GFX11 %s
7; RUN: FileCheck --enable-var-scope --check-prefixes=DBG,DBG11 %s < %t
8; REQUIRES: asserts
9
10; FIXME: Verifier error with xnack enabled.
11
12; DBG-LABEL: cluster_load_cluster_store:
13
14; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8
15; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8
16; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
17; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
18; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
19; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
20
21; DBG: Cluster ld/st SU(1) - SU(2)
22
23; DBG: Cluster ld/st SU([[L1:[0-9]+]]) - SU([[L2:[0-9]+]])
24; DBG: Cluster ld/st SU([[L2]]) - SU([[L3:[0-9]+]])
25; DBG: Cluster ld/st SU([[L3]]) - SU([[L4:[0-9]+]])
26
27; DBG11: Cluster ld/st SU([[S1:[0-9]+]]) - SU([[S2:[0-9]+]])
28; DBG11: Cluster ld/st SU([[S2]]) - SU([[S3:[0-9]+]])
29; DBG11: Cluster ld/st SU([[S3]]) - SU([[S4:[0-9]+]])
30
31; DBG-NOT: Cluster ld/st
32
33define amdgpu_kernel void @cluster_load_cluster_store(i32* noalias %lb, i32* noalias %sb) {
34; GFX9-LABEL: cluster_load_cluster_store:
35; GFX9:       ; %bb.0: ; %bb
36; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
37; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x2c
38; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
39; GFX9-NEXT:    v_mov_b32_e32 v0, s2
40; GFX9-NEXT:    v_mov_b32_e32 v1, s3
41; GFX9-NEXT:    flat_load_dword v2, v[0:1]
42; GFX9-NEXT:    flat_load_dword v3, v[0:1] offset:8
43; GFX9-NEXT:    flat_load_dword v4, v[0:1] offset:16
44; GFX9-NEXT:    flat_load_dword v5, v[0:1] offset:24
45; GFX9-NEXT:    v_mov_b32_e32 v0, s0
46; GFX9-NEXT:    v_mov_b32_e32 v1, s1
47; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
48; GFX9-NEXT:    flat_store_dword v[0:1], v2
49; GFX9-NEXT:    flat_store_dword v[0:1], v3 offset:8
50; GFX9-NEXT:    flat_store_dword v[0:1], v4 offset:16
51; GFX9-NEXT:    flat_store_dword v[0:1], v5 offset:24
52; GFX9-NEXT:    s_endpgm
53;
54; GFX10-LABEL: cluster_load_cluster_store:
55; GFX10:       ; %bb.0: ; %bb
56; GFX10-NEXT:    s_clause 0x1
57; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
58; GFX10-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
59; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
60; GFX10-NEXT:    s_add_u32 s0, s2, 8
61; GFX10-NEXT:    s_addc_u32 s1, s3, 0
62; GFX10-NEXT:    s_add_u32 s6, s2, 16
63; GFX10-NEXT:    v_mov_b32_e32 v3, s1
64; GFX10-NEXT:    s_addc_u32 s7, s3, 0
65; GFX10-NEXT:    v_mov_b32_e32 v0, s2
66; GFX10-NEXT:    v_mov_b32_e32 v2, s0
67; GFX10-NEXT:    s_add_u32 s0, s2, 24
68; GFX10-NEXT:    v_mov_b32_e32 v1, s3
69; GFX10-NEXT:    s_addc_u32 s1, s3, 0
70; GFX10-NEXT:    v_mov_b32_e32 v4, s6
71; GFX10-NEXT:    v_mov_b32_e32 v5, s7
72; GFX10-NEXT:    v_mov_b32_e32 v7, s1
73; GFX10-NEXT:    v_mov_b32_e32 v6, s0
74; GFX10-NEXT:    s_clause 0x3
75; GFX10-NEXT:    flat_load_dword v8, v[0:1]
76; GFX10-NEXT:    flat_load_dword v9, v[2:3]
77; GFX10-NEXT:    flat_load_dword v10, v[4:5]
78; GFX10-NEXT:    flat_load_dword v11, v[6:7]
79; GFX10-NEXT:    s_add_u32 s0, s4, 8
80; GFX10-NEXT:    s_addc_u32 s1, s5, 0
81; GFX10-NEXT:    v_mov_b32_e32 v0, s4
82; GFX10-NEXT:    v_mov_b32_e32 v3, s1
83; GFX10-NEXT:    v_mov_b32_e32 v2, s0
84; GFX10-NEXT:    s_add_u32 s0, s4, 16
85; GFX10-NEXT:    s_addc_u32 s1, s5, 0
86; GFX10-NEXT:    s_add_u32 s2, s4, 24
87; GFX10-NEXT:    v_mov_b32_e32 v1, s5
88; GFX10-NEXT:    s_addc_u32 s3, s5, 0
89; GFX10-NEXT:    v_mov_b32_e32 v5, s1
90; GFX10-NEXT:    v_mov_b32_e32 v4, s0
91; GFX10-NEXT:    v_mov_b32_e32 v7, s3
92; GFX10-NEXT:    v_mov_b32_e32 v6, s2
93; GFX10-NEXT:    s_waitcnt vmcnt(3) lgkmcnt(3)
94; GFX10-NEXT:    flat_store_dword v[0:1], v8
95; GFX10-NEXT:    s_waitcnt vmcnt(2) lgkmcnt(3)
96; GFX10-NEXT:    flat_store_dword v[2:3], v9
97; GFX10-NEXT:    s_waitcnt vmcnt(1) lgkmcnt(3)
98; GFX10-NEXT:    flat_store_dword v[4:5], v10
99; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(3)
100; GFX10-NEXT:    flat_store_dword v[6:7], v11
101; GFX10-NEXT:    s_endpgm
102;
103; GFX11-LABEL: cluster_load_cluster_store:
104; GFX11:       ; %bb.0: ; %bb
105; GFX11-NEXT:    s_clause 0x1
106; GFX11-NEXT:    s_load_b64 s[2:3], s[0:1], 0x24
107; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x2c
108; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
109; GFX11-NEXT:    v_mov_b32_e32 v0, s2
110; GFX11-NEXT:    v_mov_b32_e32 v1, s3
111; GFX11-NEXT:    s_clause 0x3
112; GFX11-NEXT:    flat_load_b32 v2, v[0:1]
113; GFX11-NEXT:    flat_load_b32 v3, v[0:1] offset:8
114; GFX11-NEXT:    flat_load_b32 v4, v[0:1] offset:16
115; GFX11-NEXT:    flat_load_b32 v5, v[0:1] offset:24
116; GFX11-NEXT:    v_mov_b32_e32 v0, s0
117; GFX11-NEXT:    v_mov_b32_e32 v1, s1
118; GFX11-NEXT:    s_waitcnt vmcnt(3) lgkmcnt(3)
119; GFX11-NEXT:    flat_store_b32 v[0:1], v2
120; GFX11-NEXT:    s_waitcnt vmcnt(2) lgkmcnt(3)
121; GFX11-NEXT:    flat_store_b32 v[0:1], v3 offset:8
122; GFX11-NEXT:    s_waitcnt vmcnt(1) lgkmcnt(3)
123; GFX11-NEXT:    flat_store_b32 v[0:1], v4 offset:16
124; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(3)
125; GFX11-NEXT:    flat_store_b32 v[0:1], v5 offset:24
126; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
127; GFX11-NEXT:    s_endpgm
128bb:
129  %la0 = getelementptr inbounds i32, i32* %lb, i32 0
130  %ld0 = load i32, i32* %la0
131  %la1 = getelementptr inbounds i32, i32* %lb, i32 2
132  %ld1 = load i32, i32* %la1
133  %la2 = getelementptr inbounds i32, i32* %lb, i32 4
134  %ld2 = load i32, i32* %la2
135  %la3 = getelementptr inbounds i32, i32* %lb, i32 6
136  %ld3 = load i32, i32* %la3
137
138  %sa0 = getelementptr inbounds i32, i32* %sb, i32 0
139  store i32 %ld0, i32* %sa0
140  %sa1 = getelementptr inbounds i32, i32* %sb, i32 2
141  store i32 %ld1, i32* %sa1
142  %sa2 = getelementptr inbounds i32, i32* %sb, i32 4
143  store i32 %ld2, i32* %sa2
144  %sa3 = getelementptr inbounds i32, i32* %sb, i32 6
145  store i32 %ld3, i32* %sa3
146
147  ret void
148}
149
150; DBG-LABEL: cluster_load_valu_cluster_store:
151
152; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8
153; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8
154; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
155; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
156; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
157; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
158
159; DBG: Cluster ld/st SU(1) - SU(2)
160
161; DBG: Cluster ld/st SU([[L1:[0-9]+]]) - SU([[L2:[0-9]+]])
162; DBG: Cluster ld/st SU([[L2]]) - SU([[L3:[0-9]+]])
163; DBG: Cluster ld/st SU([[L3]]) - SU([[L4:[0-9]+]])
164
165; DBG11: Cluster ld/st SU([[S1:[0-9]+]]) - SU([[S2:[0-9]+]])
166; DBG11: Cluster ld/st SU([[S2]]) - SU([[S3:[0-9]+]])
167; DBG11: Cluster ld/st SU([[S3]]) - SU([[S4:[0-9]+]])
168
169; DBG-NOT: Cluster ld/st
170
171define amdgpu_kernel void @cluster_load_valu_cluster_store(i32* noalias %lb, i32* noalias %sb) {
172; GFX9-LABEL: cluster_load_valu_cluster_store:
173; GFX9:       ; %bb.0: ; %bb
174; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
175; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x2c
176; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
177; GFX9-NEXT:    v_mov_b32_e32 v0, s2
178; GFX9-NEXT:    v_mov_b32_e32 v1, s3
179; GFX9-NEXT:    flat_load_dword v2, v[0:1]
180; GFX9-NEXT:    flat_load_dword v3, v[0:1] offset:8
181; GFX9-NEXT:    flat_load_dword v4, v[0:1] offset:16
182; GFX9-NEXT:    flat_load_dword v5, v[0:1] offset:24
183; GFX9-NEXT:    v_mov_b32_e32 v0, s0
184; GFX9-NEXT:    v_mov_b32_e32 v1, s1
185; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
186; GFX9-NEXT:    flat_store_dword v[0:1], v2
187; GFX9-NEXT:    v_add_u32_e32 v2, 1, v3
188; GFX9-NEXT:    flat_store_dword v[0:1], v4 offset:16
189; GFX9-NEXT:    flat_store_dword v[0:1], v2 offset:8
190; GFX9-NEXT:    flat_store_dword v[0:1], v5 offset:24
191; GFX9-NEXT:    s_endpgm
192;
193; GFX10-LABEL: cluster_load_valu_cluster_store:
194; GFX10:       ; %bb.0: ; %bb
195; GFX10-NEXT:    s_clause 0x1
196; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
197; GFX10-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
198; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
199; GFX10-NEXT:    s_add_u32 s0, s2, 8
200; GFX10-NEXT:    s_addc_u32 s1, s3, 0
201; GFX10-NEXT:    s_add_u32 s6, s2, 16
202; GFX10-NEXT:    v_mov_b32_e32 v3, s1
203; GFX10-NEXT:    v_mov_b32_e32 v2, s0
204; GFX10-NEXT:    s_addc_u32 s7, s3, 0
205; GFX10-NEXT:    s_add_u32 s0, s2, 24
206; GFX10-NEXT:    v_mov_b32_e32 v0, s2
207; GFX10-NEXT:    s_addc_u32 s1, s3, 0
208; GFX10-NEXT:    v_mov_b32_e32 v1, s3
209; GFX10-NEXT:    v_mov_b32_e32 v4, s6
210; GFX10-NEXT:    v_mov_b32_e32 v5, s7
211; GFX10-NEXT:    flat_load_dword v6, v[2:3]
212; GFX10-NEXT:    v_mov_b32_e32 v3, s1
213; GFX10-NEXT:    v_mov_b32_e32 v2, s0
214; GFX10-NEXT:    s_clause 0x2
215; GFX10-NEXT:    flat_load_dword v8, v[0:1]
216; GFX10-NEXT:    flat_load_dword v9, v[4:5]
217; GFX10-NEXT:    flat_load_dword v10, v[2:3]
218; GFX10-NEXT:    s_add_u32 s0, s4, 8
219; GFX10-NEXT:    s_addc_u32 s1, s5, 0
220; GFX10-NEXT:    s_add_u32 s2, s4, 16
221; GFX10-NEXT:    v_mov_b32_e32 v3, s1
222; GFX10-NEXT:    s_addc_u32 s3, s5, 0
223; GFX10-NEXT:    v_mov_b32_e32 v0, s4
224; GFX10-NEXT:    v_mov_b32_e32 v2, s0
225; GFX10-NEXT:    s_add_u32 s0, s4, 24
226; GFX10-NEXT:    v_mov_b32_e32 v1, s5
227; GFX10-NEXT:    v_mov_b32_e32 v5, s3
228; GFX10-NEXT:    s_addc_u32 s1, s5, 0
229; GFX10-NEXT:    v_mov_b32_e32 v4, s2
230; GFX10-NEXT:    s_waitcnt vmcnt(3) lgkmcnt(3)
231; GFX10-NEXT:    v_add_nc_u32_e32 v11, 1, v6
232; GFX10-NEXT:    v_mov_b32_e32 v7, s1
233; GFX10-NEXT:    v_mov_b32_e32 v6, s0
234; GFX10-NEXT:    s_waitcnt vmcnt(2) lgkmcnt(2)
235; GFX10-NEXT:    flat_store_dword v[0:1], v8
236; GFX10-NEXT:    s_waitcnt vmcnt(1) lgkmcnt(2)
237; GFX10-NEXT:    flat_store_dword v[4:5], v9
238; GFX10-NEXT:    flat_store_dword v[2:3], v11
239; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(3)
240; GFX10-NEXT:    flat_store_dword v[6:7], v10
241; GFX10-NEXT:    s_endpgm
242;
243; GFX11-LABEL: cluster_load_valu_cluster_store:
244; GFX11:       ; %bb.0: ; %bb
245; GFX11-NEXT:    s_clause 0x1
246; GFX11-NEXT:    s_load_b64 s[2:3], s[0:1], 0x24
247; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x2c
248; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
249; GFX11-NEXT:    v_mov_b32_e32 v0, s2
250; GFX11-NEXT:    v_mov_b32_e32 v1, s3
251; GFX11-NEXT:    s_clause 0x3
252; GFX11-NEXT:    flat_load_b32 v2, v[0:1] offset:8
253; GFX11-NEXT:    flat_load_b32 v3, v[0:1]
254; GFX11-NEXT:    flat_load_b32 v4, v[0:1] offset:16
255; GFX11-NEXT:    flat_load_b32 v5, v[0:1] offset:24
256; GFX11-NEXT:    v_mov_b32_e32 v0, s0
257; GFX11-NEXT:    v_mov_b32_e32 v1, s1
258; GFX11-NEXT:    s_waitcnt vmcnt(3) lgkmcnt(3)
259; GFX11-NEXT:    v_add_nc_u32_e32 v2, 1, v2
260; GFX11-NEXT:    s_waitcnt vmcnt(2) lgkmcnt(2)
261; GFX11-NEXT:    s_clause 0x1
262; GFX11-NEXT:    flat_store_b32 v[0:1], v3
263; GFX11-NEXT:    flat_store_b32 v[0:1], v2 offset:8
264; GFX11-NEXT:    s_waitcnt vmcnt(1) lgkmcnt(3)
265; GFX11-NEXT:    flat_store_b32 v[0:1], v4 offset:16
266; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(3)
267; GFX11-NEXT:    flat_store_b32 v[0:1], v5 offset:24
268; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
269; GFX11-NEXT:    s_endpgm
270bb:
271  %la0 = getelementptr inbounds i32, i32* %lb, i32 0
272  %ld0 = load i32, i32* %la0
273  %la1 = getelementptr inbounds i32, i32* %lb, i32 2
274  %ld1 = load i32, i32* %la1
275  %la2 = getelementptr inbounds i32, i32* %lb, i32 4
276  %ld2 = load i32, i32* %la2
277  %la3 = getelementptr inbounds i32, i32* %lb, i32 6
278  %ld3 = load i32, i32* %la3
279
280  %sa0 = getelementptr inbounds i32, i32* %sb, i32 0
281  store i32 %ld0, i32* %sa0
282  %sa1 = getelementptr inbounds i32, i32* %sb, i32 2
283  %add = add i32 %ld1, 1
284  store i32 %add, i32* %sa1
285  %sa2 = getelementptr inbounds i32, i32* %sb, i32 4
286  store i32 %ld2, i32* %sa2
287  %sa3 = getelementptr inbounds i32, i32* %sb, i32 6
288  store i32 %ld3, i32* %sa3
289
290  ret void
291}
292
293; Cluster loads from the same texture with different coordinates
294; DBG-LABEL: cluster_image_load:
295; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
296; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
297; DBG: {{^}}Cluster ld/st [[SU1:SU\([0-9]+\)]] - [[SU2:SU\([0-9]+\)]]
298; DBG: {{^}}[[SU1]]: {{.*}} IMAGE_LOAD
299; DBG: {{^}}[[SU2]]: {{.*}} IMAGE_LOAD
300define amdgpu_ps void @cluster_image_load(<8 x i32> inreg %src, <8 x i32> inreg %dst, i32 %x, i32 %y) {
301; GFX9-LABEL: cluster_image_load:
302; GFX9:       ; %bb.0: ; %entry
303; GFX9-NEXT:    v_add_u32_e32 v2, 1, v0
304; GFX9-NEXT:    v_add_u32_e32 v3, 1, v1
305; GFX9-NEXT:    v_add_u32_e32 v6, 2, v0
306; GFX9-NEXT:    v_add_u32_e32 v7, 2, v1
307; GFX9-NEXT:    image_load v[2:5], v[2:3], s[0:7] dmask:0xf unorm
308; GFX9-NEXT:    image_load v[6:9], v[6:7], s[0:7] dmask:0xf unorm
309; GFX9-NEXT:    s_waitcnt vmcnt(0)
310; GFX9-NEXT:    v_add_f32_e32 v5, v5, v9
311; GFX9-NEXT:    v_add_f32_e32 v4, v4, v8
312; GFX9-NEXT:    v_add_f32_e32 v3, v3, v7
313; GFX9-NEXT:    v_add_f32_e32 v2, v2, v6
314; GFX9-NEXT:    image_store v[2:5], v[0:1], s[8:15] dmask:0xf unorm
315; GFX9-NEXT:    s_endpgm
316;
317; GFX10-LABEL: cluster_image_load:
318; GFX10:       ; %bb.0: ; %entry
319; GFX10-NEXT:    v_add_nc_u32_e32 v10, 1, v0
320; GFX10-NEXT:    v_add_nc_u32_e32 v11, 1, v1
321; GFX10-NEXT:    v_add_nc_u32_e32 v12, 2, v0
322; GFX10-NEXT:    v_add_nc_u32_e32 v13, 2, v1
323; GFX10-NEXT:    s_clause 0x1
324; GFX10-NEXT:    image_load v[2:5], v[10:11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
325; GFX10-NEXT:    image_load v[6:9], v[12:13], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
326; GFX10-NEXT:    s_waitcnt vmcnt(0)
327; GFX10-NEXT:    v_add_f32_e32 v5, v5, v9
328; GFX10-NEXT:    v_add_f32_e32 v4, v4, v8
329; GFX10-NEXT:    v_add_f32_e32 v3, v3, v7
330; GFX10-NEXT:    v_add_f32_e32 v2, v2, v6
331; GFX10-NEXT:    image_store v[2:5], v[0:1], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
332; GFX10-NEXT:    s_endpgm
333;
334; GFX11-LABEL: cluster_image_load:
335; GFX11:       ; %bb.0: ; %entry
336; GFX11-NEXT:    v_add_nc_u32_e32 v2, 1, v0
337; GFX11-NEXT:    v_add_nc_u32_e32 v3, 1, v1
338; GFX11-NEXT:    v_add_nc_u32_e32 v6, 2, v0
339; GFX11-NEXT:    v_add_nc_u32_e32 v7, 2, v1
340; GFX11-NEXT:    s_clause 0x1
341; GFX11-NEXT:    image_load v[2:5], v[2:3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
342; GFX11-NEXT:    image_load v[6:9], v[6:7], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
343; GFX11-NEXT:    s_waitcnt vmcnt(0)
344; GFX11-NEXT:    v_add_f32_e32 v5, v5, v9
345; GFX11-NEXT:    v_add_f32_e32 v4, v4, v8
346; GFX11-NEXT:    v_add_f32_e32 v3, v3, v7
347; GFX11-NEXT:    v_add_f32_e32 v2, v2, v6
348; GFX11-NEXT:    image_store v[2:5], v[0:1], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
349; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
350; GFX11-NEXT:    s_endpgm
351entry:
352  %x1 = add i32 %x, 1
353  %y1 = add i32 %y, 1
354  %val1 = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 %x1, i32 %y1, <8 x i32> %src, i32 0, i32 0)
355  %x2 = add i32 %x, 2
356  %y2 = add i32 %y, 2
357  %val2 = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 %x2, i32 %y2, <8 x i32> %src, i32 0, i32 0)
358  %val = fadd fast <4 x float> %val1, %val2
359  call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %val, i32 15, i32 %x, i32 %y, <8 x i32> %dst, i32 0, i32 0)
360  ret void
361}
362
363; Don't cluster loads from different textures
364; DBG-LABEL: no_cluster_image_load:
365; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
366; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
367; DBG-NOT: {{^}}Cluster ld/st
368define amdgpu_ps void @no_cluster_image_load(<8 x i32> inreg %src1, <8 x i32> inreg %src2, <8 x i32> inreg %dst, i32 %x, i32 %y) {
369; GFX9-LABEL: no_cluster_image_load:
370; GFX9:       ; %bb.0: ; %entry
371; GFX9-NEXT:    v_mov_b32_e32 v2, 0
372; GFX9-NEXT:    image_load_mip v[3:6], v[0:2], s[0:7] dmask:0xf unorm
373; GFX9-NEXT:    image_load_mip v[7:10], v[0:2], s[8:15] dmask:0xf unorm
374; GFX9-NEXT:    s_waitcnt vmcnt(0)
375; GFX9-NEXT:    v_add_f32_e32 v6, v6, v10
376; GFX9-NEXT:    v_add_f32_e32 v5, v5, v9
377; GFX9-NEXT:    v_add_f32_e32 v4, v4, v8
378; GFX9-NEXT:    v_add_f32_e32 v3, v3, v7
379; GFX9-NEXT:    image_store v[3:6], v[0:1], s[16:23] dmask:0xf unorm
380; GFX9-NEXT:    s_endpgm
381;
382; GFX10-LABEL: no_cluster_image_load:
383; GFX10:       ; %bb.0: ; %entry
384; GFX10-NEXT:    v_mov_b32_e32 v10, 0
385; GFX10-NEXT:    image_load_mip v[2:5], [v0, v1, v10], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
386; GFX10-NEXT:    image_load_mip v[6:9], [v0, v1, v10], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
387; GFX10-NEXT:    s_waitcnt vmcnt(0)
388; GFX10-NEXT:    v_add_f32_e32 v5, v5, v9
389; GFX10-NEXT:    v_add_f32_e32 v4, v4, v8
390; GFX10-NEXT:    v_add_f32_e32 v3, v3, v7
391; GFX10-NEXT:    v_add_f32_e32 v2, v2, v6
392; GFX10-NEXT:    image_store v[2:5], v[0:1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
393; GFX10-NEXT:    s_endpgm
394;
395; GFX11-LABEL: no_cluster_image_load:
396; GFX11:       ; %bb.0: ; %entry
397; GFX11-NEXT:    v_mov_b32_e32 v6, 0
398; GFX11-NEXT:    image_load_mip v[2:5], [v0, v1, v6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
399; GFX11-NEXT:    image_load_mip v[6:9], [v0, v1, v6], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
400; GFX11-NEXT:    s_waitcnt vmcnt(0)
401; GFX11-NEXT:    v_add_f32_e32 v5, v5, v9
402; GFX11-NEXT:    v_add_f32_e32 v4, v4, v8
403; GFX11-NEXT:    v_add_f32_e32 v3, v3, v7
404; GFX11-NEXT:    v_add_f32_e32 v2, v2, v6
405; GFX11-NEXT:    image_store v[2:5], v[0:1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
406; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
407; GFX11-NEXT:    s_endpgm
408entry:
409  %val1 = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 15, i32 %x, i32 %y, i32 0, <8 x i32> %src1, i32 0, i32 0)
410  %val2 = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 15, i32 %x, i32 %y, i32 0, <8 x i32> %src2, i32 0, i32 0)
411  %val = fadd fast <4 x float> %val1, %val2
412  call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %val, i32 15, i32 %x, i32 %y, <8 x i32> %dst, i32 0, i32 0)
413  ret void
414}
415
416; Cluster loads from the same texture and sampler with different coordinates
417; DBG-LABEL: cluster_image_sample:
418; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
419; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
420; DBG: {{^}}Cluster ld/st [[SU1:SU\([0-9]+\)]] - [[SU2:SU\([0-9]+\)]]
421; DBG: {{^}}[[SU1]]: {{.*}} IMAGE_SAMPLE
422; DBG: {{^}}[[SU2]]: {{.*}} IMAGE_SAMPLE
423define amdgpu_ps void @cluster_image_sample(<8 x i32> inreg %src, <4 x i32> inreg %smp, <8 x i32> inreg %dst, i32 %x, i32 %y) {
424; GFX9-LABEL: cluster_image_sample:
425; GFX9:       ; %bb.0: ; %entry
426; GFX9-NEXT:    v_cvt_f32_i32_e32 v8, v0
427; GFX9-NEXT:    v_cvt_f32_i32_e32 v9, v1
428; GFX9-NEXT:    v_mov_b32_e32 v4, 0
429; GFX9-NEXT:    v_mov_b32_e32 v5, v4
430; GFX9-NEXT:    v_add_f32_e32 v2, 1.0, v8
431; GFX9-NEXT:    v_add_f32_e32 v3, 1.0, v9
432; GFX9-NEXT:    v_mov_b32_e32 v6, v4
433; GFX9-NEXT:    v_mov_b32_e32 v7, v4
434; GFX9-NEXT:    v_add_f32_e32 v8, 2.0, v8
435; GFX9-NEXT:    v_add_f32_e32 v9, 2.0, v9
436; GFX9-NEXT:    v_mov_b32_e32 v10, 1.0
437; GFX9-NEXT:    v_mov_b32_e32 v11, v10
438; GFX9-NEXT:    v_mov_b32_e32 v12, v10
439; GFX9-NEXT:    v_mov_b32_e32 v13, v10
440; GFX9-NEXT:    image_sample_d v[2:5], v[2:7], s[0:7], s[8:11] dmask:0xf
441; GFX9-NEXT:    image_sample_d v[6:9], v[8:13], s[0:7], s[8:11] dmask:0xf
442; GFX9-NEXT:    s_waitcnt vmcnt(0)
443; GFX9-NEXT:    v_add_f32_e32 v5, v5, v9
444; GFX9-NEXT:    v_add_f32_e32 v4, v4, v8
445; GFX9-NEXT:    v_add_f32_e32 v3, v3, v7
446; GFX9-NEXT:    v_add_f32_e32 v2, v2, v6
447; GFX9-NEXT:    image_store v[2:5], v[0:1], s[12:19] dmask:0xf unorm
448; GFX9-NEXT:    s_endpgm
449;
450; GFX10-LABEL: cluster_image_sample:
451; GFX10:       ; %bb.0: ; %entry
452; GFX10-NEXT:    v_cvt_f32_i32_e32 v8, v0
453; GFX10-NEXT:    v_cvt_f32_i32_e32 v9, v1
454; GFX10-NEXT:    v_mov_b32_e32 v4, 0
455; GFX10-NEXT:    v_mov_b32_e32 v10, 1.0
456; GFX10-NEXT:    v_add_f32_e32 v2, 1.0, v8
457; GFX10-NEXT:    v_add_f32_e32 v3, 1.0, v9
458; GFX10-NEXT:    v_mov_b32_e32 v5, v4
459; GFX10-NEXT:    v_mov_b32_e32 v6, v4
460; GFX10-NEXT:    v_mov_b32_e32 v7, v4
461; GFX10-NEXT:    v_add_f32_e32 v8, 2.0, v8
462; GFX10-NEXT:    v_add_f32_e32 v9, 2.0, v9
463; GFX10-NEXT:    v_mov_b32_e32 v11, v10
464; GFX10-NEXT:    v_mov_b32_e32 v12, v10
465; GFX10-NEXT:    v_mov_b32_e32 v13, v10
466; GFX10-NEXT:    s_clause 0x1
467; GFX10-NEXT:    image_sample_d v[14:17], v[2:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
468; GFX10-NEXT:    image_sample_d v[18:21], v[8:13], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
469; GFX10-NEXT:    s_waitcnt vmcnt(0)
470; GFX10-NEXT:    v_add_f32_e32 v5, v17, v21
471; GFX10-NEXT:    v_add_f32_e32 v4, v16, v20
472; GFX10-NEXT:    v_add_f32_e32 v3, v15, v19
473; GFX10-NEXT:    v_add_f32_e32 v2, v14, v18
474; GFX10-NEXT:    image_store v[2:5], v[0:1], s[12:19] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
475; GFX10-NEXT:    s_endpgm
476;
477; GFX11-LABEL: cluster_image_sample:
478; GFX11:       ; %bb.0: ; %entry
479; GFX11-NEXT:    v_cvt_f32_i32_e32 v8, v0
480; GFX11-NEXT:    v_cvt_f32_i32_e32 v9, v1
481; GFX11-NEXT:    v_mov_b32_e32 v4, 0
482; GFX11-NEXT:    v_mov_b32_e32 v10, 1.0
483; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
484; GFX11-NEXT:    v_add_f32_e32 v2, 1.0, v8
485; GFX11-NEXT:    v_add_f32_e32 v3, 1.0, v9
486; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4)
487; GFX11-NEXT:    v_mov_b32_e32 v5, v4
488; GFX11-NEXT:    v_mov_b32_e32 v6, v4
489; GFX11-NEXT:    v_mov_b32_e32 v7, v4
490; GFX11-NEXT:    v_add_f32_e32 v8, 2.0, v8
491; GFX11-NEXT:    v_add_f32_e32 v9, 2.0, v9
492; GFX11-NEXT:    v_mov_b32_e32 v11, v10
493; GFX11-NEXT:    v_mov_b32_e32 v12, v10
494; GFX11-NEXT:    v_mov_b32_e32 v13, v10
495; GFX11-NEXT:    s_clause 0x1
496; GFX11-NEXT:    image_sample_d v[2:5], v[2:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
497; GFX11-NEXT:    image_sample_d v[6:9], v[8:13], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
498; GFX11-NEXT:    s_waitcnt vmcnt(0)
499; GFX11-NEXT:    v_add_f32_e32 v5, v5, v9
500; GFX11-NEXT:    v_add_f32_e32 v4, v4, v8
501; GFX11-NEXT:    v_add_f32_e32 v3, v3, v7
502; GFX11-NEXT:    v_add_f32_e32 v2, v2, v6
503; GFX11-NEXT:    image_store v[2:5], v[0:1], s[12:19] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
504; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
505; GFX11-NEXT:    s_endpgm
506entry:
507  %s = sitofp i32 %x to float
508  %t = sitofp i32 %y to float
509  %s1 = fadd float %s, 1.0
510  %t1 = fadd float %t, 1.0
511  %val1 = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32(i32 15, float %s1, float %t1, float 0.0, float 0.0, float 0.0, float 0.0, <8 x i32> %src, <4 x i32> %smp, i1 false, i32 0, i32 0)
512  %s2 = fadd float %s, 2.0
513  %t2 = fadd float %t, 2.0
514  %val2 = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32(i32 15, float %s2, float %t2, float 1.0, float 1.0, float 1.0, float 1.0, <8 x i32> %src, <4 x i32> %smp, i1 false, i32 0, i32 0)
515  %val = fadd fast <4 x float> %val1, %val2
516  call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %val, i32 15, i32 %x, i32 %y, <8 x i32> %dst, i32 0, i32 0)
517  ret void
518}
519
520declare <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg)
521declare <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg)
522declare <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32(i32, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32)
523declare void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg)
524