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Searched refs:IsStore (Results 1 – 25 of 34) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp158 bool IsStore = false; in emitInstruction() local
160 &IsStore); in emitInstruction()
166 bool MaskAfter = IsSPFirstOperand && !IsStore; in emitInstruction()
211 bool *IsStore) { in isBasePlusOffsetMemoryAccess() argument
212 if (IsStore) in isBasePlusOffsetMemoryAccess()
213 *IsStore = false; in isBasePlusOffsetMemoryAccess()
243 if (IsStore) in isBasePlusOffsetMemoryAccess()
244 *IsStore = true; in isBasePlusOffsetMemoryAccess()
251 if (IsStore) in isBasePlusOffsetMemoryAccess()
252 *IsStore = true; in isBasePlusOffsetMemoryAccess()
H A DMipsMCNaCl.h21 bool *IsStore = nullptr);
/llvm-project-15.0.7/bolt/lib/Passes/
H A DStackAvailableExpressions.cpp40 if (FIE->IsStore == true && FIE->IsSimple == true) { in preflight()
89 if (FIEX->IsStore == true && FIEY->IsStore == true && in doesXKillsY()
101 if (FIEY && FIEY->IsStore == true && FIEY->IsStoreFromReg) in doesXKillsY()
126 if (FIE->IsStore == true && FIE->IsSimple == true) in computeNext()
H A DShrinkWrapping.cpp62 if (!FIE->IsStore || !FIE->IsStoreFromReg || in analyzeSaves()
677 bool IsStore = false; in performChanges() local
697 else if (IsStore) in performChanges()
1486 Item.FIEToInsert.IsStore) { in compNextAux()
1553 bool IsStore = false; in insertUpdatedCFI() local
1768 if ((Item.FIEToInsert.IsStore && in processInsertion()
1773 if (Item.FIEToInsert.IsStore) in processInsertion()
1778 if (Item.FIEToInsert.IsStore) in processInsertion()
1837 if (Item.FIEToInsert.IsStore) in processInsertionsList()
1866 Item.FIEToInsert.IsStore) in processInsertionsList()
[all …]
H A DFrameAnalysis.cpp80 OS << "FrameIndexEntry<IsLoad: " << FIE.IsLoad << ", IsStore: " << FIE.IsStore in operator <<()
128 Inst, FIE.IsLoad, FIE.IsStore, FIE.IsStoreFromReg, Reg, SrcImm, in decodeFrameAccess()
133 if (IsIndexed || (!FIE.Size && (FIE.IsLoad || FIE.IsStore))) { in decodeFrameAccess()
141 assert(FIE.Size != 0 || (!FIE.IsLoad && !FIE.IsStore)); in decodeFrameAccess()
H A DStackReachingUses.cpp95 FIEX->IsStore == true && FIEY->IsLoad == true && in doesXKillsY()
H A DValidateInternalCalls.cpp236 if (!BC.MIB->isStackAccess(*TargetInst, FIE.IsLoad, FIE.IsStore, in analyzeFunction()
H A DFrameOptimizer.cpp104 assert(FIEY->IsStore && FIEY->IsSimple); in removeUnnecessaryLoads()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp75 unsigned int IsStore : 1; member
367 SwapVector[VecIdx].IsStore = 1; in gatherVectorInstructions()
373 SwapVector[VecIdx].IsStore = 1; in gatherVectorInstructions()
683 SwapVector[UseIdx].IsStore) { in recordUnoptimizableWebs()
700 !SwapVector[UseIdx].IsStore) { in recordUnoptimizableWebs()
705 if (SwapVector[UseOfUseIdx].IsStore) { in recordUnoptimizableWebs()
722 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) { in recordUnoptimizableWebs()
730 SwapVector[DefIdx].IsStore) { in recordUnoptimizableWebs()
796 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) { in markSwapsForRemoval()
1008 if (SwapVector[EntryIdx].IsStore) in dumpSwapVector()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kCollapseMOVEMPass.cpp204 bool IsStore = false) { in ProcessMI() argument
209 if (State.isStore() == IsStore && State.getBase() == Reg && in ProcessMI()
218 return ProcessMI(MBB, MI, State, Mask, Offset, Reg, IsStore); in ProcessMI()
227 IsStore ? State.setStore() : State.setLoad(); in ProcessMI()
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXInstrFormats.td36 bit IsStore = false;
52 let TSFlags{6...6} = IsStore;
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp406 bool IsStore = Ldst->mayStore(); in canHoistLoadStoreTo() local
413 if (IsStore && MI->mayLoad()) in canHoistLoadStoreTo()
455 bool IsStore = Ldst.mayStore(); in changeToAddrMode() local
465 if (IsStore) { in changeToAddrMode()
472 if (IsStore) in changeToAddrMode()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td822 bit IsStore = ?;
1130 let IsStore = true;
1135 let IsStore = true;
1142 let IsStore = true;
1147 let IsStore = true;
1153 let IsStore = true;
1159 let IsStore = true;
1165 let IsStore = true;
1170 let IsStore = true;
1175 let IsStore = true;
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp1165 bool IsStore = MI->mayStore(); in spillVGPRtoAGPR() local
1169 unsigned Dst = IsStore ? Reg : ValueReg; in spillVGPRtoAGPR()
1170 unsigned Src = IsStore ? ValueReg : Reg; in spillVGPRtoAGPR()
1202 bool IsStore = MI->mayStore(); in buildMUBUFOffsetLoadStore() local
1205 int LoadStoreOp = IsStore ? in buildMUBUFOffsetLoadStore()
1235 bool IsStore = TII->get(LoadStoreOp).mayStore(); in getFlatScratchSpillOpcode() local
1243 LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORD_SADDR in getFlatScratchSpillOpcode()
1283 bool IsStore = Desc->mayStore(); in buildSpillLoadStore() local
1489 unsigned SrcDstRegState = getDefRegState(!IsStore); in buildSpillLoadStore()
1499 bool NeedSuperRegDef = e > 1 && IsStore && i == 0; in buildSpillLoadStore()
[all …]
H A DAMDGPUInstructions.td422 let IsStore = 1;
506 let IsStore = 1, AddressSpaces = !cast<AddressSpaceList>("StoreAddress_"#as).AddrSpaces in {
531 } // End let IsStore = 1, AddressSpaces = ...
607 let IsStore = 1;
612 let IsStore = 1;
H A DSIInstrInfo.td507 let IsStore = 1;
513 let IsStore = 1;
519 let IsStore = 1;
525 let IsStore = 1;
532 let IsStore = 1;
549 let IsStore = 1;
555 let IsStore = 1;
575 let IsStore = 1;
581 let IsStore = 1;
652 let IsStore = 1;
[all …]
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DX86FoldTablesEmitter.cpp108 bool IsStore = false; member in __anone539286b0111::X86FoldTablesEmitter::X86FoldTableEntry
126 if (IsStore) in print()
413 Result.IsStore = true; in addEntryWithFlags()
/llvm-project-15.0.7/bolt/include/bolt/Passes/
H A DFrameAnalysis.h26 bool IsStore; member
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp467 bool IsStore = Entry.WideOpc == ARM::t2STR_POST; in ReduceLoadStore() local
468 Register Rt = MI->getOperand(IsStore ? 1 : 0).getReg(); in ReduceLoadStore()
469 Register Rn = MI->getOperand(IsStore ? 0 : 1).getReg(); in ReduceLoadStore()
486 .addReg(Rt, IsStore ? 0 : RegState::Define); in ReduceLoadStore()
/llvm-project-15.0.7/bolt/lib/Target/X86/
H A DX86MCPlusBuilder.cpp1036 bool isStackAccess(const MCInst &Inst, bool &IsLoad, bool &IsStore, in isStackAccess() argument
1043 IsStore = true; in isStackAccess()
1060 IsStore = false; in isStackAccess()
1077 bool IsStore; in isStackAccess() member
1092 bool IsStore = MCII.mayStore(); in isStackAccess() local
1094 if (!IsLoad && !IsStore) { in isStackAccess()
1095 I = {0, IsLoad, IsStore, false, false}; in isStackAccess()
1099 I = {Sz, IsLoad, IsStore, false, false}; in isStackAccess()
1134 IsStore = I.IsStore; in isStackAccess()
1151 } else if (I.IsStore) { in isStackAccess()
[all …]
/llvm-project-15.0.7/clang/include/clang/Basic/
H A Darm_sve.td186 def IsStore : FlagType<0x00004000>;
549 def SVST1 : MInst<"svst1[_{d}]", "vPpd", "csilUcUsUiUlhfd", [IsStore], MemEltTyDefault, "aarch6…
550 def SVST1B_S : MInst<"svst1b[_{d}]", "vPAd", "sil", [IsStore], MemEltTyInt8, "aarch6…
551 def SVST1B_U : MInst<"svst1b[_{d}]", "vPEd", "UsUiUl", [IsStore], MemEltTyInt8, "aarch6…
552 def SVST1H_S : MInst<"svst1h[_{d}]", "vPBd", "il", [IsStore], MemEltTyInt16, "aarch6…
553 def SVST1H_U : MInst<"svst1h[_{d}]", "vPFd", "UiUl", [IsStore], MemEltTyInt16, "aarch6…
554 def SVST1W_S : MInst<"svst1w[_{d}]", "vPCd", "l", [IsStore], MemEltTyInt32, "aarch6…
555 def SVST1W_U : MInst<"svst1w[_{d}]", "vPGd", "Ul", [IsStore], MemEltTyInt32, "aarch6…
567 …def SVST1_BF : MInst<"svst1[_{d}]", "vPpd", "b", [IsStore], MemEltTyDefault, "aarch64_s…
568 …def SVST1_VNUM_BF : MInst<"svst1_vnum[_{d}]", "vPpld", "b", [IsStore], MemEltTyDefault, "aarch64_s…
[all …]
H A DTargetBuiltins.h262 bool isStore() const { return Flags & IsStore; } in isStore()
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCGAtomic.cpp1344 bool IsStore = E->getOp() == AtomicExpr::AO__c11_atomic_store || in EmitAtomicExpr() local
1367 if (IsStore) in EmitAtomicExpr()
1379 if (IsLoad || IsStore) in EmitAtomicExpr()
1404 if (!IsStore) in EmitAtomicExpr()
1408 if (!IsLoad && !IsStore) in EmitAtomicExpr()
1425 if (!IsStore) { in EmitAtomicExpr()
1443 if (!IsLoad && !IsStore) { in EmitAtomicExpr()
/llvm-project-15.0.7/llvm/test/TableGen/
H A Daddress-space-patfrags.td94 let IsStore = 1;
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonExpandCondsets.cpp823 bool IsLoad = TheI.mayLoad(), IsStore = TheI.mayStore(); in canMoveMemTo() local
824 if (!IsLoad && !IsStore) in canMoveMemTo()
846 bool Conflict = (L && IsStore) || S; in canMoveMemTo()

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