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Searched refs:IntVT (Results 1 – 22 of 22) sorted by relevance

/llvm-project-15.0.7/llvm/unittests/CodeGen/
H A DAArch64SelectionDAGTest.cpp119 auto IntVT = EVT::getIntegerVT(Context, 8); in TEST_F() local
156 auto IntVT = EVT::getIntegerVT(Context, 8); in TEST_F() local
170 auto IntVT = EVT::getIntegerVT(Context, 8); in TEST_F() local
237 auto IntVT = EVT::getIntegerVT(Context, 8); in TEST_F() local
256 auto IntVT = EVT::getIntegerVT(Context, 8); in TEST_F() local
276 auto IntVT = EVT::getIntegerVT(Context, 8); in TEST_F() local
296 auto IntVT = EVT::getIntegerVT(Context, 8); in TEST_F() local
320 auto IntVT = EVT::getIntegerVT(Context, 8); in TEST_F() local
340 auto IntVT = EVT::getIntegerVT(Context, 8); in TEST_F() local
431 MVT IntVT = MVT::i8; in TEST_F() local
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DValueTypes.h400 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE; in getHalfSizedIntegerVT() local
401 IntVT <= MVT::LAST_INTEGER_VALUETYPE; ++IntVT) { in getHalfSizedIntegerVT()
402 EVT HalfVT = EVT((MVT::SimpleValueType)IntVT); in getHalfSizedIntegerVT()
H A DTargetLowering.h2197 virtual bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT, in shouldUseStrictFP_TO_INT() argument
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DFunctionLoweringInfo.cpp441 EVT IntVT = ValueVTs[0]; in ComputePHILiveOutRegInfo() local
443 if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1) in ComputePHILiveOutRegInfo()
445 IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT); in ComputePHILiveOutRegInfo()
446 unsigned BitWidth = IntVT.getSizeInBits(); in ComputePHILiveOutRegInfo()
H A DTargetLowering.cpp7349 EVT IntVT = SrcVT.changeTypeToInteger(); in expandFP_TO_SINT() local
7354 SDValue Bias = DAG.getConstant(127, dl, IntVT); in expandFP_TO_SINT()
7362 ISD::SRL, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask), in expandFP_TO_SINT()
7366 SDValue Sign = DAG.getNode(ISD::SRA, dl, IntVT, in expandFP_TO_SINT()
7371 SDValue R = DAG.getNode(ISD::OR, dl, IntVT, in expandFP_TO_SINT()
7674 IntVT = EVT::getVectorVT(*DAG.getContext(), IntVT, in expandIS_FPCLASS()
7676 SDValue OpAsInt = DAG.getBitcast(IntVT, Op); in expandIS_FPCLASS()
7694 SDValue ZeroV = DAG.getConstant(0, DL, IntVT); in expandIS_FPCLASS()
7695 SDValue InfV = DAG.getConstant(Inf, DL, IntVT); in expandIS_FPCLASS()
7809 DAG.getNode(ISD::SUB, DL, IntVT, V, DAG.getConstant(1, DL, IntVT)); in expandIS_FPCLASS()
[all …]
H A DFastISel.cpp301 EVT IntVT = TLI.getPointerTy(DL); in materializeConstant() local
302 uint32_t IntBitWidth = IntVT.getSizeInBits(); in materializeConstant()
310 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, in materializeConstant()
1618 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); in selectFNeg() local
1619 if (!TLI.isTypeLegal(IntVT)) in selectFNeg()
1622 Register IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), in selectFNeg()
1628 IntVT.getSimpleVT(), ISD::XOR, IntReg, in selectFNeg()
1629 UINT64_C(1) << (VT.getSizeInBits() - 1), IntVT.getSimpleVT()); in selectFNeg()
1633 ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST, in selectFNeg()
H A DLegalizeDAG.cpp1602 EVT IntVT = SignAsInt.IntValue.getValueType(); in ExpandFCOPYSIGN() local
1603 SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT); in ExpandFCOPYSIGN()
1613 SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit, in ExpandFCOPYSIGN()
1628 EVT ShiftVT = IntVT; in ExpandFCOPYSIGN()
1656 EVT IntVT = SignAsInt.IntValue.getValueType(); in ExpandFNEG() local
1659 SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT); in ExpandFNEG()
1661 DAG.getNode(ISD::XOR, DL, IntVT, SignAsInt.IntValue, SignMask); in ExpandFNEG()
1681 EVT IntVT = ValueAsInt.IntValue.getValueType(); in ExpandFABS() local
4303 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE; in ConvertNodeToLibcall() local
4305 ++IntVT) { in ConvertNodeToLibcall()
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H A DDAGCombiner.cpp13917 SrcEltVT = IntVT; in ConstantFoldBITCASTofBUILD_VECTOR()
17753 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || in TransformFPLoadStorePair()
17754 !TLI.isOperationLegal(ISD::STORE, IntVT) || in TransformFPLoadStorePair()
22734 EVT IntVT = VT.changeVectorElementTypeToInteger(); in visitVECTOR_SHUFFLE() local
22751 if (TLI.isVectorClearMaskLegal(ClearMask, IntVT)) in visitVECTOR_SHUFFLE()
22753 VT, DAG.getVectorShuffle(IntVT, DL, DAG.getBitcast(IntVT, N0), in visitVECTOR_SHUFFLE()
22756 if (TLI.isOperationLegalOrCustom(ISD::AND, IntVT)) in visitVECTOR_SHUFFLE()
22758 VT, DAG.getNode(ISD::AND, DL, IntVT, DAG.getBitcast(IntVT, N0), in visitVECTOR_SHUFFLE()
24017 EVT IntVT = Int.getValueType(); in foldSignChangeInBitcast() local
24020 if (!IntVT.isInteger() || IntVT.isVector()) in foldSignChangeInBitcast()
[all …]
H A DLegalizeFloatTypes.cpp951 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE; in findFPToIntLibcall() local
952 IntVT <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; in findFPToIntLibcall()
953 ++IntVT) { in findFPToIntLibcall()
954 Promoted = (MVT::SimpleValueType)IntVT; in findFPToIntLibcall()
H A DSelectionDAG.cpp6603 EVT IntVT = VT.getScalarType(); in getMemsetValue() local
6604 if (!IntVT.isInteger()) in getMemsetValue()
6605 IntVT = EVT::getIntegerVT(*DAG.getContext(), IntVT.getSizeInBits()); in getMemsetValue()
6607 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, IntVT, Value); in getMemsetValue()
6612 Value = DAG.getNode(ISD::MUL, dl, IntVT, Value, in getMemsetValue()
6613 DAG.getConstant(Magic, dl, IntVT)); in getMemsetValue()
H A DSelectionDAGBuilder.cpp241 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); in getCopyFromParts() local
242 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V, CC); in getCopyFromParts()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelLowering.cpp162 for (MVT IntVT : {MVT::i32, MVT::i64}) { in initSPUActions()
164 setOperationAction(ISD::UREM, IntVT, Expand); in initSPUActions()
165 setOperationAction(ISD::SREM, IntVT, Expand); in initSPUActions()
182 setOperationAction(ISD::CTTZ, IntVT, Expand); in initSPUActions()
183 setOperationAction(ISD::ROTL, IntVT, Expand); in initSPUActions()
184 setOperationAction(ISD::ROTR, IntVT, Expand); in initSPUActions()
195 setOperationAction(ISD::CTLZ, IntVT, Act); in initSPUActions()
197 setOperationAction(ISD::CTPOP, IntVT, Act); in initSPUActions()
201 setOperationAction(ISD::AND, IntVT, Act); in initSPUActions()
202 setOperationAction(ISD::OR, IntVT, Act); in initSPUActions()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp1833 MVT IntVT = VT.changeVectorElementTypeToInteger(); in lowerFTRUNC_FCEIL_FFLOOR() local
1834 SDValue Truncated = DAG.getNode(ISD::FP_TO_SINT, DL, IntVT, Src); in lowerFTRUNC_FCEIL_FFLOOR()
1908 MVT IntVT = VT.changeVectorElementTypeToInteger(); in lowerFROUND() local
2983 EVT IntVT = FloatVT.changeVectorElementTypeToInteger(); in lowerCTLZ_CTTZ_ZERO_UNDEF() local
2984 SDValue Bitcast = DAG.getBitcast(IntVT, FloatVal); in lowerCTLZ_CTTZ_ZERO_UNDEF()
2986 SDValue Shift = DAG.getNode(ISD::SRL, DL, IntVT, Bitcast, in lowerCTLZ_CTTZ_ZERO_UNDEF()
5731 MVT IntVT = VecVT.changeVectorElementTypeToInteger(); in lowerVECTOR_REVERSE() local
5780 SplatVL = DAG.getSplatVector(IntVT, DL, VLMinus1); in lowerVECTOR_REVERSE()
5782 SplatVL = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, IntVT, DAG.getUNDEF(IntVT), in lowerVECTOR_REVERSE()
5785 SDValue VID = DAG.getNode(RISCVISD::VID_VL, DL, IntVT, Mask, VL); in lowerVECTOR_REVERSE()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp1725 EVT IntVT = MemVT.changeTypeToInteger(); in lowerKernargMemParameter() local
4840 EVT IntVT = LoadVT.changeTypeToInteger(); in lowerIntrinsicLoad() local
5722 MVT IntVT = MVT::getIntegerVT(VecSize); in lowerINSERT_VECTOR_ELT() local
5728 SDValue BFM = DAG.getNode(ISD::SHL, SL, IntVT, in lowerINSERT_VECTOR_ELT()
5733 SDValue ExtVal = DAG.getNode(ISD::BITCAST, SL, IntVT, in lowerINSERT_VECTOR_ELT()
5741 SDValue RHS = DAG.getNode(ISD::AND, SL, IntVT, in lowerINSERT_VECTOR_ELT()
5810 MVT IntVT = MVT::getIntegerVT(VecSize); in lowerEXTRACT_VECTOR_ELT() local
5817 Vec = DAG.getAnyExtOrTrunc(Src, SL, IntVT); in lowerEXTRACT_VECTOR_ELT()
5828 SDValue BC = DAG.getNode(ISD::BITCAST, SL, IntVT, Vec); in lowerEXTRACT_VECTOR_ELT()
7325 EVT IntVT = VT.changeTypeToInteger(); in LowerINTRINSIC_W_CHAIN() local
[all …]
H A DAMDGPUISelLowering.cpp1578 MVT IntVT = MVT::i32; in LowerDIVREM24() local
1598 SDValue jq = DAG.getConstant(1, DL, IntVT); in LowerDIVREM24()
1645 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq); in LowerDIVREM24()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp772 MVT IntVT = MVT::getIntegerVT(VT.getFixedSizeInBits()); in initActions() local
773 if (IntVT.isValid()) { in initActions()
775 AddPromotedToType(ISD::ATOMIC_SWAP, VT, IntVT); in initActions()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp3978 MVT IntVT = is64Bit() ? MVT::i64 : MVT::i32; in forwardMustTailParameters() local
3979 RegParmTypes.push_back(IntVT); in forwardMustTailParameters()
20821 MVT IntVT = CastToInt.getSimpleValueType(); in lowerFPToIntToFP() local
20830 IntVT != MVT::i32) in lowerFPToIntToFP()
20834 unsigned IntSize = IntVT.getSizeInBits(); in lowerFPToIntToFP()
42393 EVT IntVT = in combineBitcastvxi1() local
42395 V = DAG.getZExtOrTrunc(V, DL, IntVT); in combineBitcastvxi1()
47308 IntVT = MVT::i32; in combineCompareEqual()
49012 if (TLI.isTypeLegal(IntVT)) { in combineLoad()
52555 EVT IntVT = BV->getValueType(0); in combineVectorCompareAndMaskUnaryOp() local
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H A DX86ISelDAGToDAG.cpp1202 EVT IntVT = EVT(VecVT).changeVectorElementTypeToInteger(); in PreprocessISelDAG() local
1203 Op0 = CurDAG->getNode(ISD::BITCAST, dl, IntVT, Op0); in PreprocessISelDAG()
1204 Op1 = CurDAG->getNode(ISD::BITCAST, dl, IntVT, Op1); in PreprocessISelDAG()
1213 Res = CurDAG->getNode(Opc, dl, IntVT, Op0, Op1); in PreprocessISelDAG()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp5522 MVT IntVT = MVT::getIntegerVT(VT.getScalarSizeInBits()); in lowerINSERT_VECTOR_ELT() local
5523 MVT IntVecVT = MVT::getVectorVT(IntVT, VT.getVectorNumElements()); in lowerINSERT_VECTOR_ELT()
5526 DAG.getNode(ISD::BITCAST, DL, IntVT, Op1), Op2); in lowerINSERT_VECTOR_ELT()
5549 MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits()); in lowerEXTRACT_VECTOR_ELT() local
5550 MVT IntVecVT = MVT::getVectorVT(IntVT, VecVT.getVectorNumElements()); in lowerEXTRACT_VECTOR_ELT()
5551 SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntVT, in lowerEXTRACT_VECTOR_ELT()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp3888 EVT IntVT = SrcVT.changeVectorElementTypeToInteger(); in LowerVectorFP_TO_INT_SAT() local
3889 SDValue NativeCvt = DAG.getNode(Op.getOpcode(), DL, IntVT, SrcVal, in LowerVectorFP_TO_INT_SAT()
3890 DAG.getValueType(IntVT.getScalarType())); in LowerVectorFP_TO_INT_SAT()
3895 SDValue Min = DAG.getNode(ISD::SMIN, DL, IntVT, NativeCvt, MinC); in LowerVectorFP_TO_INT_SAT()
3898 Sat = DAG.getNode(ISD::SMAX, DL, IntVT, Min, MaxC); in LowerVectorFP_TO_INT_SAT()
3902 Sat = DAG.getNode(ISD::UMIN, DL, IntVT, NativeCvt, MinC); in LowerVectorFP_TO_INT_SAT()
7725 EVT IntVT = VT.changeTypeToInteger(); in LowerFCOPYSIGN() local
7738 IntVT = in LowerFCOPYSIGN()
7765 VecVT = IntVT; in LowerFCOPYSIGN()
14400 EVT IntVT = BV->getValueType(0); in performVectorCompareAndMaskUnaryOpCombine() local
[all …]
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp976 MVT IntVT = MVT::i32; in LowerFormalArguments() local
977 RegParmTypes.push_back(IntVT); in LowerFormalArguments()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp7620 EVT IntVT = Op.getValueType(); in LowerGET_DYNAMIC_AREA_OFFSET() local
7627 SDVTList VTs = DAG.getVTList(IntVT); in LowerGET_DYNAMIC_AREA_OFFSET()