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Searched refs:Combine (Results 1 – 25 of 83) sorted by relevance

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/llvm-project-15.0.7/flang/include/flang/Evaluate/
H A Dtraverse.h125 return Combine(x.base(), x.GetLastSymbol()); in operator()
138 return Combine(x.lower(), x.upper(), x.stride()); in operator()
142 return Combine(x.base(), x.subscript()); in operator()
145 return Combine( in operator()
150 return Combine(x.parent(), x.lower(), x.upper()); in operator()
186 return Combine(x.proc(), x.arguments()); in operator()
228 return Combine(op.left(), op.right()); in operator()
255 Result Combine(const A &x, const Bs &...ys) const { in Combine() function
259 return visitor_.Combine(visitor_(x), Combine(ys...)); in Combine()
287 static Result Combine(Result &&x, Result &&y) { in Combine() function
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H A Dtools.h656 Expr<SPECIFIC> Combine(Expr<SPECIFIC> &&x, Expr<SPECIFIC> &&y) { in Combine() function
672 Combine<OPR, Ty>(std::move(xy[0]), std::move(xy[1]))); in PromoteAndCombine()
750 return AsExpr(Combine<Add, Type<C, K>>(std::move(x), std::move(y)));
755 return AsExpr(Combine<Subtract, Type<C, K>>(std::move(x), std::move(y)));
760 return AsExpr(Combine<Multiply, Type<C, K>>(std::move(x), std::move(y)));
765 return AsExpr(Combine<Divide, Type<C, K>>(std::move(x), std::move(y)));
959 Result Combine(Result &&a, Result &&b) { in Combine() function
/llvm-project-15.0.7/llvm/test/Linker/
H A Dmodule-max-warn.ll3 ; CHECK: warning: linking module flags 'Combine Max and Warn': IDs have conflicting values ('i32 4'…
4 ; CHECK: warning: linking module flags 'Combine Warn and Max': IDs have conflicting values ('i32 5'…
7 ; CHECK: !0 = !{i32 7, !"Combine Max and Warn", i32 4}
8 ; CHECK: !1 = !{i32 7, !"Combine Warn and Max", i32 5}
11 !0 = !{i32 7, !"Combine Max and Warn", i32 2}
12 !1 = !{i32 2, !"Combine Warn and Max", i32 3}
/llvm-project-15.0.7/clang/unittests/AST/
H A DASTImporterVisibilityTest.cpp186 ::testing::Combine(
198 ::testing::Combine(
203 ::testing::Combine(
403 ::testing::Combine(
417 ::testing::Combine(
431 ::testing::Combine(
440 ::testing::Combine(
449 ::testing::Combine(
458 ::testing::Combine(
486 ::testing::Combine(
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/llvm-project-15.0.7/llvm/test/Linker/Inputs/
H A Dmodule-max-warn.ll2 !0 = !{i32 2, !"Combine Max and Warn", i32 4}
3 !1 = !{i32 7, !"Combine Warn and Max", i32 5}
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsCombine.td1 //=- MipsCombine.td - Define Mips Combine Rules --------------*- tablegen -*-=//
9 include "llvm/Target/GlobalISel/Combine.td"
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/AMDGPU/
H A Dfmul_legacy.ll22 ; Combine to fmul because the constant is finite and non-zero.
32 ; Combine to fmul because the constant is finite and non-zero, preserving fmf.
42 ; Combine to fmul because neither argument can be infinity or NaN.
H A Dfma_legacy.ll52 ; Combine to fma because the constant is finite and non-zero.
62 ; Combine to fma because the constant is finite and non-zero, preserving fmf.
72 ; Combine to fma because neither argument can be infinity or NaN.
/llvm-project-15.0.7/llvm/test/TableGen/GICombinerEmitter/
H A Ddefs-invalid.td6 include "llvm/Target/GlobalISel/Combine.td"
25 // CHECK: :[[@LINE-4]]:{{[0-9]+}}: error: Combine rules must have at least one root
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dvpadd.ll216 ; Combine vuzp+vadd->vpadd.
233 ; Combine vuzp+vadd->vpadd.
249 ; Combine vtrn+vadd->vpadd.
265 ; Combine vuzp+vaddl->vpaddl
283 ; Combine vuzp+vaddl->vpaddl
306 ; Combine vuzp+vaddl->vpaddl
345 ; Combine vuzp+vaddl->vpaddl
385 ; Combine vuzp+vaddl->vpaddl
403 ; Combine vuzp+vaddl->vpaddl
421 ; Combine vtrn+vaddl->vpaddl
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUCombine.td1 //=- AMDGPUCombine.td - Define AMDGPU Combine Rules ----------*- tablegen -*-=//
9 include "llvm/Target/GlobalISel/Combine.td"
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dearly_constfold_changes_IR.ll20 ; DETAILS: Made Modification 'Combine redundant instructions' on Function 'foo'
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dbswap-rotate.ll5 ; Combine BSWAP (lowered to rolw 8) with a second rotate.
/llvm-project-15.0.7/polly/test/Simplify/
H A Dcoalesce_3partials.ll3 ; Combine 3 partial accesses into one.
H A Dcoalesce_partial.ll3 ; Combine two partial stores (with disjoint domains) into one.
H A Dcoalesce_overlapping.ll3 ; Combine two partial stores (with overlapping domains) into one.
H A Dcoalesce_disjointelements.ll3 ; Combine four partial stores into two.
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dcombine-reg-or-const.ll3 ; The OR instruction should not be eliminated by the "OR Combine" DAG optimization.
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Hexagon/
H A Dalu32_perm.txt4 # Combine words in to doublewords
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/msa/
H A Dbitcast.ll55 ; We can't prevent the (store (bitcast X), Y) DAG Combine here because there
229 ; We can't prevent the (store (bitcast X), Y) DAG Combine here because there
353 ; We can't prevent the (bitcast (load X)) DAG Combine here because there
376 ; We can't prevent the (bitcast (load X)) DAG Combine here because there
399 ; We can't prevent the (bitcast (load X)) DAG Combine here because there
401 ; We can't prevent the (store (bitcast X), Y) DAG Combine here because there
421 ; We can't prevent the (bitcast (load X)) DAG Combine here because there
444 ; We can't prevent the (bitcast (load X)) DAG Combine here because there
467 ; We can't prevent the (bitcast (load X)) DAG Combine here because there
490 ; We can't prevent the (bitcast (load X)) DAG Combine here because there
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/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/autohvx/
H A Dvector-align-store-mask.ll6 ; Vector Combine pass generates masked stores for chunks of 128 bytes.
H A Dvector-align-addr.ll3 ; Test that the Hexagon Vector Combine pass computes the address
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64Combine.td1 //=- AArch64.td - Define AArch64 Combine Rules ---------------*- tablegen -*-=//
12 include "llvm/Target/GlobalISel/Combine.td"
/llvm-project-15.0.7/mlir/test/Dialect/SPIRV/Linking/ModuleCombiner/
H A Dbasic.mlir3 // Combine modules without the same symbols
/llvm-project-15.0.7/lld/test/MachO/
H A Dbind-opcodes.s10 ## 2/ Combine BIND_OPCODE_DO_BIND and BIND_OPCODE_ADD_ADDR_ULEB pairs.
79 ## 2/ Combine BIND_OPCODE_DO_BIND and BIND_OPCODE_ADD_ADDR_ULEB pairs.

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