AMDGPU/GlobalISel: Add clamp combine

Add clamp combine. Source is fminnum(fmaxnum(Val, 0.0), 1.0) or
fmaxnum(fminnum(Val, 1.0), 0.0) or fmed3 intrinsic with 0.0 and
1.0 as two out of three operands.

AMDGPU/GlobalISel: Add clamp combine

Add clamp combine. Source is fminnum(fmaxnum(Val, 0.0), 1.0) or
fmaxnum(fminnum(Val, 1.0), 0.0) or fmed3 intrinsic with 0.0 and
1.0 as two out of three operands.

Differential Revision: https://reviews.llvm.org/D90052

show more ...

AMDGPU/GlobalISel: Add floating point med3 combine

Add floating point version of med3 combine.
Source is fminnum(fmaxnum(Val, K0), K1) or fmaxnum(fminnum(Val, K1), K0)
where K0 and K1 are constants

AMDGPU/GlobalISel: Add floating point med3 combine

Add floating point version of med3 combine.
Source is fminnum(fmaxnum(Val, K0), K1) or fmaxnum(fminnum(Val, K1), K0)
where K0 and K1 are constants and K0 <= K1.

Differential Revision: https://reviews.llvm.org/D90051

show more ...

Code quality: Combine V_RSQ

Combine V_RCP and V_SQRT into V_RSQ on AMDGPU for GlobalISel.

Change-Id: I93c5dcb412483156a6e8b68c4085cbce83ac9703

[AMDGPU][GlobalISel] Fold G_FNEG above when users cannot fold mods

If possible fold fneg into instruction above if users cannot fold mods and we
know it will decrease instruction count.
Follows same

[AMDGPU][GlobalISel] Fold G_FNEG above when users cannot fold mods

If possible fold fneg into instruction above if users cannot fold mods and we
know it will decrease instruction count.
Follows same logic as SDAG combiner in choosing opportunities to combine.

Differential Revision: https://reviews.llvm.org/D112827

show more ...

[GlobalISel] Add combine for PTR_ADD with regbanks

Combine two G_PTR_ADDs, but keep the register bank of the constant.
That way, the combine can be used in post-regbank-select combines.

Introduce t

[GlobalISel] Add combine for PTR_ADD with regbanks

Combine two G_PTR_ADDs, but keep the register bank of the constant.
That way, the combine can be used in post-regbank-select combines.

Introduce two helper methods in CombinerHelper, getRegBank and
setRegBank that get and set an optional register bank to a register.
That way, they can be used before and after register bank selection.

Differential Revision: https://reviews.llvm.org/D103326

show more ...

AMDGPU/GlobalISel: Remove redundant G_FCANONICALIZE

Add basic version of isCanonicalized for global-isel. Copied from sdag.
Add post legalizer combine that deletes G_FCANONICALIZE when its input
is

AMDGPU/GlobalISel: Remove redundant G_FCANONICALIZE

Add basic version of isCanonicalized for global-isel. Copied from sdag.
Add post legalizer combine that deletes G_FCANONICALIZE when its input
is already Canonicalized.

Differential Revision: https://reviews.llvm.org/D96605

show more ...

AMDGPU/GlobalISel: Add integer med3 combines

Add signed and unsigned integer version of med3 combine.
Source pattern is min(max(Val, K0), K1) or max(min(Val, K1), K0)
where K0 and K1 are constants a

AMDGPU/GlobalISel: Add integer med3 combines

Add signed and unsigned integer version of med3 combine.
Source pattern is min(max(Val, K0), K1) or max(min(Val, K1), K0)
where K0 and K1 are constants and K0 <= K1. Destination is med3
that corresponds to signedness of min/max in source.

Differential Revision: https://reviews.llvm.org/D90050

show more ...

Reland AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect

Recommit bf5a5826504754788a8f1e3fec7a7dc95cda5782. Depends on
4c8fb7ddd6fa49258e0e9427e7345fb56ba522d4 which was reverted.

R

Reland AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect

Recommit bf5a5826504754788a8f1e3fec7a7dc95cda5782. Depends on
4c8fb7ddd6fa49258e0e9427e7345fb56ba522d4 which was reverted.

RegBankSelect creates zext and trunc when it selects banks for uniform i1.
Add zext_trunc_fold from generic combiner to post RegBankSelect combiner.

Differential Revision: https://reviews.llvm.org/D95432

show more ...

Revert "AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect"

This reverts commit bf5a5826504754788a8f1e3fec7a7dc95cda5782.
Also depends on now-reverted 4c8fb7ddd6fa49258e0e9427e7345fb5

Revert "AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect"

This reverts commit bf5a5826504754788a8f1e3fec7a7dc95cda5782.
Also depends on now-reverted 4c8fb7ddd6fa49258e0e9427e7345fb56ba522d4

show more ...

AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect

RegBankSelect creates zext and trunc when it selects banks for uniform i1.
Add zext_trunc_fold from generic combiner to post RegBank

AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect

RegBankSelect creates zext and trunc when it selects banks for uniform i1.
Add zext_trunc_fold from generic combiner to post RegBankSelect combiner.

Differential Revision: https://reviews.llvm.org/D95432

show more ...

[AMDGPU]: Fixes an invalid clamp selection pattern.

When running the tests on PowerPC and x86, the lit test GlobalISel/trunc.ll fails at the memory sanitize step. This seems to be due to wrong inval

[AMDGPU]: Fixes an invalid clamp selection pattern.

When running the tests on PowerPC and x86, the lit test GlobalISel/trunc.ll fails at the memory sanitize step. This seems to be due to wrong invalid logic (which matches even if it shouldn't) and likely missing variable initialisation."

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D95878

show more ...

Revert "[AMDGPU] Add a new Clamp Pattern to the GlobalISel Path."

This reverts commits 62af0305b7cc..677a3529d3e6 from D93708.
They cause failures in the sanitizer builds because of uninitialized
va

Revert "[AMDGPU] Add a new Clamp Pattern to the GlobalISel Path."

This reverts commits 62af0305b7cc..677a3529d3e6 from D93708.
They cause failures in the sanitizer builds because of uninitialized
values.

A fix is in D95878, but it might take some time until this is pushed,
so reverting the changes for now.

show more ...

Move Combiner to PreLegalize step

Added clamp i64 to i16 global isel pattern.

AMDGPU/GlobalISel: Use same builder/observer in post-legalizer-combiner

Change match/apply functions into methods of new target specific combiner
helper class. Use reference to MachineIRBuilder from

AMDGPU/GlobalISel: Use same builder/observer in post-legalizer-combiner

Change match/apply functions into methods of new target specific combiner
helper class. Use reference to MachineIRBuilder from helper instead of
constructing new MachineIRBuilder each time new instruction needs to made.
Allows correct tracking of newly created instructions.

Differential Revision: https://reviews.llvm.org/D90623

show more ...

[GlobalISel] Rewrite the elide-br-by-swapping-icmp-ops combine to do less.

This combine previously tried to take sequences like:
%cond = G_ICMP pred, a, b
G_BRCOND %cond, %truebb
G_BR %falsebb

[GlobalISel] Rewrite the elide-br-by-swapping-icmp-ops combine to do less.

This combine previously tried to take sequences like:
%cond = G_ICMP pred, a, b
G_BRCOND %cond, %truebb
G_BR %falsebb
%truebb:
...
%falsebb:
...

and by inverting the compare predicate and swapping branch targets, delete the
G_BR and instead have a single conditional branch to the falsebb. Since in an
earlier patch we have a combine to fold not(icmp) into just an inverted icmp,
we don't need this combine to do as much. This patch instead generalizes the
combine by just looking for:
G_BRCOND %cond, %truebb
G_BR %falsebb
%truebb:
...
%falsebb:
...

and then inverting the condition using a not (xor). The xor can be folded away
in a separate combine. This change also lets us avoid some optimization code
in the IRTranslator.

I also think that deleting G_BRs in the combiner is unnecessary. That's
something that targets can decide to do at selection time and could simplify
generic code in future.

Differential Revision: https://reviews.llvm.org/D86664

show more ...

AMDGPU/GlobalISel: Remove hack for combines forming illegal extloads

Previously we weren't adding the LegalizerInfo to the post-legalizer
combiner. Since that's fixed, we don't need to try to filter

AMDGPU/GlobalISel: Remove hack for combines forming illegal extloads

Previously we weren't adding the LegalizerInfo to the post-legalizer
combiner. Since that's fixed, we don't need to try to filter out the
one case that was breaking.

show more ...

AMDGPU/GlobalISel: Add stub reg-bank aware combiner pass

AMDGPU/GlobalISel: Combines for V_CVT_F32_UBYTE[0-3]

Ports the existing DAG combines, minus the simplify demanded bits
which seems to have no equivalent now. Without these, this isn't
particularly h

AMDGPU/GlobalISel: Combines for V_CVT_F32_UBYTE[0-3]

Ports the existing DAG combines, minus the simplify demanded bits
which seems to have no equivalent now. Without these, this isn't
particularly helpful in most of the IR sample cases.

show more ...

AMDGPU/GlobalISel: Work around forming illegal zextload after legalize

Selection would fail after the post legalize combiner put an illegal
zextload back together.

The base combiner has parameter t

AMDGPU/GlobalISel: Work around forming illegal zextload after legalize

Selection would fail after the post legalize combiner put an illegal
zextload back together.

The base combiner has parameter to only allow legal operations, but
they appear to not be used. I also don't see a nice way to remove a
single entry from all_combines, so just hack around this.

show more ...

AMDGPU/GlobalISel: Form CVT_F32_UBYTE0

AMDGPU/GlobalISel: Introduce post-legalize combiner

The current set of custom combines are only really useful after
legalization, so move them there. There is a lot of overlap in the
boilerplate her

AMDGPU/GlobalISel: Introduce post-legalize combiner

The current set of custom combines are only really useful after
legalization, so move them there. There is a lot of overlap in the
boilerplate here, but I think we do want a pretty different set of
combines before and after legalize. I think we will want a lot of
overlap between the post-legalize and a post-regbankselect combiner.

show more ...

AMDGPU/GlobalISel: Combine FMIN_LEGACY/FMAX_LEGACY

Try out using combine definition rules.

This really should be a post-legalizer combine, but the combiner pass
is currently pre-legalize. Most of t

AMDGPU/GlobalISel: Combine FMIN_LEGACY/FMAX_LEGACY

Try out using combine definition rules.

This really should be a post-legalizer combine, but the combiner pass
is currently pre-legalize. Most of the target combines are really
post-legalize, so we should probably move the pass.

show more ...

AMDGPU/GlobalISel: Add pre-legalize combiner pass

Just copy the AArch64 pass as-is for now, except for removing the
memcpy handling.