Changes in AMDGPUCombine.td

0b34ffe4 - AMDGPU/GlobalISel: Add clamp combine

Fri, 03 Dec 2021 11:14:28 +0000

AMDGPU/GlobalISel: Add clamp combineAdd clamp combine. Source is fminnum(fmaxnum(Val, 0.0), 1.0) orfmaxnum(fminnum(Val, 1.0), 0.0) or fmed3 intrinsic with 0.0 and1.0 as two out of three operands.Differential Revision: https://reviews.llvm.org/D90052 List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AMDGPUCombine.td

ec54867d - AMDGPU/GlobalISel: Add floating point med3 combine

Fri, 03 Dec 2021 11:06:14 +0000

AMDGPU/GlobalISel: Add floating point med3 combineAdd floating point version of med3 combine.Source is fminnum(fmaxnum(Val, K0), K1) or fmaxnum(fminnum(Val, K1), K0)where K0 and K1 are constants and K0 <= K1.Differential Revision: https://reviews.llvm.org/D90051 List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AMDGPUCombine.td

ca57b80c - Code quality: Combine V_RSQ

Mon, 20 Sep 2021 14:05:45 +0000

Code quality: Combine V_RSQCombine V_RCP and V_SQRT into V_RSQ on AMDGPU for GlobalISel.Change-Id: I93c5dcb412483156a6e8b68c4085cbce83ac9703 List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AMDGPUCombine.td

db6bc2ab - [AMDGPU][GlobalISel] Fold G_FNEG above when users cannot fold mods

Wed, 17 Nov 2021 13:19:45 +0000

[AMDGPU][GlobalISel] Fold G_FNEG above when users cannot fold modsIf possible fold fneg into instruction above if users cannot fold mods and weknow it will decrease instruction count.Follows same logic as SDAG combiner in choosing opportunities to combine.Differential Revision: https://reviews.llvm.org/D112827 List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AMDGPUCombine.td

fbae3463 - [GlobalISel] Add combine for PTR_ADD with regbanks

Tue, 17 Aug 2021 11:58:16 +0000

[GlobalISel] Add combine for PTR_ADD with regbanksCombine two G_PTR_ADDs, but keep the register bank of the constant.That way, the combine can be used in post-regbank-select combines.Introduce two helper methods in CombinerHelper, getRegBank andsetRegBank that get and set an optional register bank to a register.That way, they can be used before and after register bank selection.Differential Revision: https://reviews.llvm.org/D103326 List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AMDGPUCombine.td

fb7be0d9 - AMDGPU/GlobalISel: Remove redundant G_FCANONICALIZE

Tue, 27 Apr 2021 10:21:57 +0000

AMDGPU/GlobalISel: Remove redundant G_FCANONICALIZEAdd basic version of isCanonicalized for global-isel. Copied from sdag.Add post legalizer combine that deletes G_FCANONICALIZE when its inputis already Canonicalized.Differential Revision: https://reviews.llvm.org/D96605 List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AMDGPUCombine.td

4a9bc598 - AMDGPU/GlobalISel: Add integer med3 combines

Tue, 27 Apr 2021 09:51:22 +0000

AMDGPU/GlobalISel: Add integer med3 combinesAdd signed and unsigned integer version of med3 combine.Source pattern is min(max(Val, K0), K1) or max(min(Val, K1), K0)where K0 and K1 are constants and K0 <= K1. Destination is med3that corresponds to signedness of min/max in source.Differential Revision: https://reviews.llvm.org/D90050 List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AMDGPUCombine.td

36beaa3b - Reland AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect

Thu, 04 Mar 2021 13:40:31 +0000

Reland AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelectRecommit bf5a5826504754788a8f1e3fec7a7dc95cda5782. Depends on4c8fb7ddd6fa49258e0e9427e7345fb56ba522d4 which was reverted.RegBankSelect creates zext and trunc when it selects banks for uniform i1.Add zext_trunc_fold from generic combiner to post RegBankSelect combiner.Differential Revision: https://reviews.llvm.org/D95432 List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AMDGPUCombine.td

e68de60b - Revert "AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect"

Thu, 04 Mar 2021 15:16:11 +0000

Revert "AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect"This reverts commit bf5a5826504754788a8f1e3fec7a7dc95cda5782.Also depends on now-reverted 4c8fb7ddd6fa49258e0e9427e7345fb56ba522d4 List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AMDGPUCombine.td

bf5a5826 - AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect

Thu, 04 Mar 2021 13:40:31 +0000

AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelectRegBankSelect creates zext and trunc when it selects banks for uniform i1.Add zext_trunc_fold from generic combiner to post RegBankSelect combiner.Differential Revision: https://reviews.llvm.org/D95432 List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AMDGPUCombine.td

f89f6d1e - [AMDGPU]: Fixes an invalid clamp selection pattern.

Tue, 02 Feb 2021 17:01:48 +0000

[AMDGPU]: Fixes an invalid clamp selection pattern.When running the tests on PowerPC and x86, the lit test GlobalISel/trunc.ll fails at the memory sanitize step. This seems to be due to wrong invalid logic (which matches even if it shouldn't) and likely missing variable initialisation."Reviewed By: arsenmDifferential Revision: https://reviews.llvm.org/D95878 List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AMDGPUCombine.td

d49efdc9 - Revert "[AMDGPU] Add a new Clamp Pattern to the GlobalISel Path."

Wed, 03 Feb 2021 10:00:30 +0000

Revert "[AMDGPU] Add a new Clamp Pattern to the GlobalISel Path."This reverts commits 62af0305b7cc..677a3529d3e6 from D93708.They cause failures in the sanitizer builds because of uninitializedvalues.A fix is in D95878, but it might take some time until this is pushed,so reverting the changes for now. List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AMDGPUCombine.td

cdfd9b3b - Move Combiner to PreLegalize step

Mon, 11 Jan 2021 13:50:28 +0000

Move Combiner to PreLegalize step List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AMDGPUCombine.td

62af0305 - Added clamp i64 to i16 global isel pattern.

Tue, 22 Dec 2020 13:37:49 +0000

Added clamp i64 to i16 global isel pattern. List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AMDGPUCombine.td

0031418d - AMDGPU/GlobalISel: Use same builder/observer in post-legalizer-combiner

Tue, 03 Nov 2020 08:23:56 +0000

AMDGPU/GlobalISel: Use same builder/observer in post-legalizer-combinerChange match/apply functions into methods of new target specific combinerhelper class. Use reference to MachineIRBuilder from helper instead ofconstructing new MachineIRBuilder each time new instruction needs to made.Allows correct tracking of newly created instructions.Differential Revision: https://reviews.llvm.org/D90623 List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AMDGPUCombine.td

cc76da7a - [GlobalISel] Rewrite the elide-br-by-swapping-icmp-ops combine to do less.

Mon, 24 Aug 2020 17:46:50 +0000

[GlobalISel] Rewrite the elide-br-by-swapping-icmp-ops combine to do less.This combine previously tried to take sequences like: %cond = G_ICMP pred, a, b G_BRCOND %cond, %truebb G_BR %falsebb%truebb: ...%falsebb: ...and by inverting the compare predicate and swapping branch targets, delete theG_BR and instead have a single conditional branch to the falsebb. Since in anearlier patch we have a combine to fold not(icmp) into just an inverted icmp,we don't need this combine to do as much. This patch instead generalizes thecombine by just looking for: G_BRCOND %cond, %truebb G_BR %falsebb%truebb: ...%falsebb: ...and then inverting the condition using a not (xor). The xor can be folded awayin a separate combine. This change also lets us avoid some optimization codein the IRTranslator.I also think that deleting G_BRs in the combiner is unnecessary. That'ssomething that targets can decide to do at selection time and could simplifygeneric code in future.Differential Revision: https://reviews.llvm.org/D86664 List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AMDGPUCombine.td

9e8d59a9 - AMDGPU/GlobalISel: Remove hack for combines forming illegal extloads

Wed, 19 Aug 2020 17:59:11 +0000

AMDGPU/GlobalISel: Remove hack for combines forming illegal extloadsPreviously we weren't adding the LegalizerInfo to the post-legalizercombiner. Since that's fixed, we don't need to try to filter out theone case that was breaking. List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AMDGPUCombine.td

a8ca0ec2 - AMDGPU/GlobalISel: Add stub reg-bank aware combiner pass

Sun, 31 May 2020 23:58:55 +0000

AMDGPU/GlobalISel: Add stub reg-bank aware combiner pass List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AMDGPUCombine.td

0ba40d4c - AMDGPU/GlobalISel: Combines for V_CVT_F32_UBYTE[0-3]

Sun, 29 Mar 2020 16:34:35 +0000

AMDGPU/GlobalISel: Combines for V_CVT_F32_UBYTE[0-3]Ports the existing DAG combines, minus the simplify demanded bitswhich seems to have no equivalent now. Without these, this isn'tparticularly helpful in most of the IR sample cases. List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AMDGPUCombine.td

cf29333f - AMDGPU/GlobalISel: Work around forming illegal zextload after legalize

Sun, 05 Apr 2020 21:48:55 +0000

AMDGPU/GlobalISel: Work around forming illegal zextload after legalizeSelection would fail after the post legalize combiner put an illegalzextload back together.The base combiner has parameter to only allow legal operations, butthey appear to not be used. I also don't see a nice way to remove asingle entry from all_combines, so just hack around this. List of files: /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AMDGPUCombine.td