1; RUN: llc -march=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s
2
3target triple = "hexagon"
4
5; Test the the store mask is adjusted for gaps between sections. The
6; Vector Combine pass generates masked stores for chunks of 128 bytes.
7; The masked store must be shifted if the first store in a section
8; is not a multiple of 128 bytes. This test checks that two masks
9; are created, and the second mask is used in a masked store.
10
11; CHECK: [[REG:r[0-9]+]] = ##.LCPI0_1
12; CHECK: [[VREG1:v[0-9]+]] = vmem([[REG]]+#0)
13; CHECK: [[VREG2:v[0-9]+]] = vlalign([[VREG1]],v{{[0-9]+}},r{{[0-9]+}})
14; CHECK: [[QREG:q[0-3]+]] = vand([[VREG2]],r{{[0-9]+}})
15; CHECK: if ([[QREG]]) vmem({{.*}}) = v{{[0-9]+}}
16
17define dllexport void @f0(i32* %a0) local_unnamed_addr #0 {
18b0:
19  br label %b1
20
21b1:                                               ; preds = %b1, %b0
22  %v0 = or i32 -1, 40
23  %v1 = getelementptr inbounds i32, i32* %a0, i32 %v0
24  %v2 = bitcast i32* %v1 to <8 x i32>*
25  store <8 x i32> undef, <8 x i32>* %v2, align 32
26  %v3 = or i32 0, 48
27  %v4 = getelementptr inbounds i32, i32* %a0, i32 %v3
28  %v5 = bitcast i32* %v4 to <8 x i32>*
29  store <8 x i32> undef, <8 x i32>* %v5, align 64
30  br i1 undef, label %b2, label %b1
31
32b2:                                               ; preds = %b1
33  ret void
34}
35
36attributes #0 = { "target-features"="+hvxv66,+hvx-length128b" }
37