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Searched refs:supported_reset (Results 1 – 25 of 28) sorted by relevance

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/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_vpe.h82 uint32_t supported_reset; member
H A Damdgpu_sdma.h132 uint32_t supported_reset; member
H A Damdgpu_jpeg.h140 uint32_t supported_reset; member
H A Damdgpu_vpe.c383 adev->vpe.supported_reset = in vpe_sw_init()
887 return amdgpu_show_reset_mask(buf, adev->vpe.supported_reset); in amdgpu_get_vpe_reset_mask()
H A Damdgpu_vcn.h355 uint32_t supported_reset; member
H A Djpeg_v3_0.c135 adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE; in jpeg_v3_0_sw_init()
H A Djpeg_v5_0_0.c124 adev->jpeg.supported_reset = in jpeg_v5_0_0_sw_init()
H A Damdgpu_jpeg.c433 return amdgpu_show_reset_mask(buf, adev->jpeg.supported_reset); in amdgpu_get_jpeg_reset_mask()
H A Dsdma_v5_2.c1360 adev->sdma.supported_reset = in sdma_v5_2_sw_init()
1368 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in sdma_v5_2_sw_init()
1372 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in sdma_v5_2_sw_init()
H A Damdgpu_sdma.c474 return amdgpu_show_reset_mask(buf, adev->sdma.supported_reset); in amdgpu_get_sdma_reset_mask()
H A Djpeg_v2_0.c121 adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE; in jpeg_v2_0_sw_init()
H A Djpeg_v2_5.c170 adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE; in jpeg_v2_5_sw_init()
H A Djpeg_v4_0.c146 adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE; in jpeg_v4_0_sw_init()
H A Djpeg_v4_0_5.c178 adev->jpeg.supported_reset = in jpeg_v4_0_5_sw_init()
H A Dsdma_v4_4_2.c1494 adev->sdma.supported_reset = in sdma_v4_4_2_sw_init()
1671 if (!(adev->sdma.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) in sdma_v4_4_2_reset_queue()
2373 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in sdma_v4_4_2_update_reset_mask()
H A Djpeg_v5_0_1.c194 adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE; in jpeg_v5_0_1_sw_init()
H A Damdgpu_device.c7131 ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset) in amdgpu_show_reset_mask() argument
7135 if (supported_reset == 0) { in amdgpu_show_reset_mask()
7142 if (supported_reset & AMDGPU_RESET_TYPE_SOFT_RESET) in amdgpu_show_reset_mask()
7145 if (supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE) in amdgpu_show_reset_mask()
7148 if (supported_reset & AMDGPU_RESET_TYPE_PER_PIPE) in amdgpu_show_reset_mask()
7151 if (supported_reset & AMDGPU_RESET_TYPE_FULL) in amdgpu_show_reset_mask()
H A Dsdma_v7_0.c1367 adev->sdma.supported_reset = in sdma_v7_0_sw_init()
1369 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in sdma_v7_0_sw_init()
H A Dsdma_v6_0.c1354 adev->sdma.supported_reset = in sdma_v6_0_sw_init()
1361 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in sdma_v6_0_sw_init()
H A Dsdma_v5_0.c1455 adev->sdma.supported_reset = in sdma_v5_0_sw_init()
1462 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; in sdma_v5_0_sw_init()
H A Dvcn_v5_0_1.c143 adev->vcn.supported_reset = in vcn_v5_0_1_sw_init()
H A Djpeg_v4_0_3.c208 adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE; in jpeg_v4_0_3_sw_init()
H A Dvcn_v5_0_0.c200 adev->vcn.supported_reset = in vcn_v5_0_0_sw_init()
H A Damdgpu_vcn.c1337 return amdgpu_show_reset_mask(buf, adev->vcn.supported_reset); in amdgpu_get_vcn_reset_mask()
H A Damdgpu.h1496 ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset);

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