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Revision tags: v6.15, v6.15-rc7, v6.15-rc6, v6.15-rc5 |
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4aaffc85 |
| 01-May-2025 |
Alex Deucher <[email protected]> |
drm/amdgpu: fix pm notifier handling
Set the s3/s0ix and s4 flags in the pm notifier so that we can skip the resource evictions properly in pm prepare based on whether we are suspending or hibernati
drm/amdgpu: fix pm notifier handling
Set the s3/s0ix and s4 flags in the pm notifier so that we can skip the resource evictions properly in pm prepare based on whether we are suspending or hibernating. Drop the eviction as processes are not frozen at this time, we we can end up getting stuck trying to evict VRAM while applications continue to submit work which causes the buffers to get pulled back into VRAM.
v2: Move suspend flags out of pm notifier (Mario)
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4178 Fixes: 2965e6355dcd ("drm/amd: Add Suspend/Hibernate notification callback support") Cc: Mario Limonciello <[email protected]> Reviewed-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]> (cherry picked from commit 06f2dcc241e7e5c681f81fbc46cacdf4bfd7d6d7) Cc: [email protected]
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d0ce1aaa |
| 01-May-2025 |
Alex Deucher <[email protected]> |
Revert "drm/amd: Stop evicting resources on APUs in suspend"
This reverts commit 3a9626c816db901def438dc2513622e281186d39.
This breaks S4 because we end up setting the s3/s0ix flags even when we ar
Revert "drm/amd: Stop evicting resources on APUs in suspend"
This reverts commit 3a9626c816db901def438dc2513622e281186d39.
This breaks S4 because we end up setting the s3/s0ix flags even when we are entering s4 since prepare is used by both flows. The causes both the S3/s0ix and s4 flags to be set which breaks several checks in the driver which assume they are mutually exclusive.
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3634 Cc: Mario Limonciello <[email protected]> Reviewed-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]> (cherry picked from commit ce8f7d95899c2869b47ea6ce0b3e5bf304b2fff4) Cc: [email protected]
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Revision tags: v6.15-rc4, v6.15-rc3, v6.15-rc2 |
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| #
e7afa85a |
| 08-Apr-2025 |
ZhenGuo Yin <[email protected]> |
drm/amdgpu: fix warning of drm_mm_clean
Kernel doorbell BOs needs to be freed before ttm_fini.
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4145 Fixes: 54c30d2a8def ("drm/amdgpu: create
drm/amdgpu: fix warning of drm_mm_clean
Kernel doorbell BOs needs to be freed before ttm_fini.
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4145 Fixes: 54c30d2a8def ("drm/amdgpu: create kernel doorbell pages") Acked-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: ZhenGuo Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]> (cherry picked from commit 39938a8ed979e398faa3791a47e282c82bcc6f04) Cc: [email protected]
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35a54408 |
| 06-Apr-2025 |
Alex Deucher <[email protected]> |
drm/amdgpu: cancel gfx idle work in device suspend for s0ix
This is normally handled in the gfx IP suspend callbacks, but for S0ix, those are skipped because we don't want to touch gfx. So handle i
drm/amdgpu: cancel gfx idle work in device suspend for s0ix
This is normally handled in the gfx IP suspend callbacks, but for S0ix, those are skipped because we don't want to touch gfx. So handle it in device suspend.
Fixes: b9467983b774 ("drm/amdgpu: add dynamic workload profile switching for gfx10") Fixes: 963537ca2325 ("drm/amdgpu: add dynamic workload profile switching for gfx11") Fixes: 5f95a1549555 ("drm/amdgpu: add dynamic workload profile switching for gfx12") Reviewed-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]> (cherry picked from commit 906ad451675155380c1dc1881a244ebde8e8df0a) Cc: [email protected]
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Revision tags: v6.15-rc1, v6.14, v6.14-rc7, v6.14-rc6, v6.14-rc5, v6.14-rc4, v6.14-rc3, v6.14-rc2 |
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| #
1bb1314d |
| 06-Feb-2025 |
Christian König <[email protected]> |
drm/amdgpu: add isolation trace point
Note when we switch from one isolation owner to another.
Signed-off-by: Christian König <[email protected]> Acked-by: Srinivasan Shanmugam <srinivasan.s
drm/amdgpu: add isolation trace point
Note when we switch from one isolation owner to another.
Signed-off-by: Christian König <[email protected]> Acked-by: Srinivasan Shanmugam <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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Revision tags: v6.14-rc1, v6.13 |
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| #
bd22e44a |
| 15-Jan-2025 |
Christian König <[email protected]> |
drm/amdgpu: rework how isolation is enforced v2
Limiting the number of available VMIDs to enforce isolation causes some issues with gang submit and applying certain HW workarounds which require mult
drm/amdgpu: rework how isolation is enforced v2
Limiting the number of available VMIDs to enforce isolation causes some issues with gang submit and applying certain HW workarounds which require multiple VMIDs to work correctly.
So instead start to track all submissions to the relevant engines in a per partition data structure and use the dma_fences of the submissions to enforce isolation similar to what a VMID limit does.
v2: use ~0l for jobs without isolation to distinct it from kernel submissions which uses NULL for the owner. Add some warning when we are OOM.
Signed-off-by: Christian König <[email protected]> Acked-by: Srinivasan Shanmugam <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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d7f5c13e |
| 18-Mar-2025 |
Ellen Pan <[email protected]> |
drm/amdgpu: Enable amdgpu_ras_resume for gfx 9.5.0
This enables ras to be resumed after gpu recovery on mi350 sriov.
Signed-off-by: Ellen Pan <[email protected]> Reviewed-by: Ahmad Rehman <Ahmad.Re
drm/amdgpu: Enable amdgpu_ras_resume for gfx 9.5.0
This enables ras to be resumed after gpu recovery on mi350 sriov.
Signed-off-by: Ellen Pan <[email protected]> Reviewed-by: Ahmad Rehman <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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9c05636c |
| 17-Mar-2025 |
Victor Skvortsov <[email protected]> |
drm/amdgpu: Skip pcie_replay_count sysfs creation for VF
VFs cannot read the NAK_COUNTER register. This information is only available through PMFW metrics.
Signed-off-by: Victor Skvortsov <victor.s
drm/amdgpu: Skip pcie_replay_count sysfs creation for VF
VFs cannot read the NAK_COUNTER register. This information is only available through PMFW metrics.
Signed-off-by: Victor Skvortsov <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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ca6575a3 |
| 12-Mar-2025 |
Alex Deucher <[email protected]> |
drm/amdgpu/vcn: fix ref counting for ring based profile handling
We need to make sure the workload profile ref counts are balanced. This isn't currently the case because we can increment the count
drm/amdgpu/vcn: fix ref counting for ring based profile handling
We need to make sure the workload profile ref counts are balanced. This isn't currently the case because we can increment the count on submissions, but the decrement may be delayed as work comes in. Track when we enable the workload profile so the references are balanced.
v2: switch to a mutex and active flag v3: fix mutex init
Fixes: 1443dd3c67f6 ("drm/amd/pm: fix and simplify workload handling") Cc: Yang Wang <[email protected]> Cc: Kenneth Feng <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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553673a3 |
| 12-Mar-2025 |
Alex Deucher <[email protected]> |
drm/amdgpu/gfx: fix ref counting for ring based profile handling
We need to make sure the workload profile ref counts are balanced. This isn't currently the case because we can increment the count
drm/amdgpu/gfx: fix ref counting for ring based profile handling
We need to make sure the workload profile ref counts are balanced. This isn't currently the case because we can increment the count on submissions, but the decrement may be delayed as work comes in. Track when we enable the workload profile so the references are balanced.
v2: switch to a mutex and active flag v3: fix mutex init
Fixes: 8fdb3958e396 ("drm/amdgpu/gfx: add ring helpers for setting workload profile") Cc: Yang Wang <[email protected]> Cc: Kenneth Feng <[email protected]> Tested-by: Kenneth Feng <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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0d9a9509 |
| 14-Jan-2025 |
Christian König <[email protected]> |
drm/amdgpu: grab an additional reference on the gang fence v2
We keep the gang submission fence around in adev, make sure that it stays alive.
v2: fix memory leak on retry
Signed-off-by: Christian
drm/amdgpu: grab an additional reference on the gang fence v2
We keep the gang submission fence around in adev, make sure that it stays alive.
v2: fix memory leak on retry
Signed-off-by: Christian König <[email protected]> Acked-by: Srinivasan Shanmugam <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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b5aaa82e |
| 14-Mar-2025 |
Flora Cui <[email protected]> |
drm/amdgpu: release xcp_mgr on exit
Free on driver cleanup.
Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Flora Cui <[email protected]> Signed-off-by: Alex Deucher <alexander.deucher@
drm/amdgpu: release xcp_mgr on exit
Free on driver cleanup.
Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Flora Cui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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Revision tags: v6.13-rc7, v6.13-rc6, v6.13-rc5, v6.13-rc4, v6.13-rc3, v6.13-rc2, v6.13-rc1, v6.12, v6.12-rc7, v6.12-rc6, v6.12-rc5, v6.12-rc4, v6.12-rc3, v6.12-rc2, v6.12-rc1 |
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| #
9deacd6c |
| 25-Sep-2024 |
Alex Deucher <[email protected]> |
drm/amdgpu: don't free conflicting apertures for non-display devices
PCI_CLASS_ACCELERATOR_PROCESSING devices won't ever be the sysfb, so there is no need to free conflicting apertures.
Reviewed-by
drm/amdgpu: don't free conflicting apertures for non-display devices
PCI_CLASS_ACCELERATOR_PROCESSING devices won't ever be the sysfb, so there is no need to free conflicting apertures.
Reviewed-by: Kent Russell <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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| #
35750679 |
| 06-Feb-2025 |
Lijo Lazar <[email protected]> |
drm/amdgpu: Calculate IP specific xgmi bandwidth
Use IP version specific xgmi speed/width for bandwidth calculation.
Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Jonathan Kim <jonath
drm/amdgpu: Calculate IP specific xgmi bandwidth
Use IP version specific xgmi speed/width for bandwidth calculation.
Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Jonathan Kim <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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a91d91b6 |
| 26-Feb-2025 |
Tony Yi <[email protected]> |
drm/amdgpu: Add support for CPERs on virtualization
Add support for CPERs on VFs.
VFs do not receive PMFW messages directly; as such, they need to query them from the host. To avoid hitting host ev
drm/amdgpu: Add support for CPERs on virtualization
Add support for CPERs on VFs.
VFs do not receive PMFW messages directly; as such, they need to query them from the host. To avoid hitting host event guard, CPER queries need to be rate limited. CPER queries share the same RAS telemetry buffer as error count query, so a mutex protecting the shared buffer was added as well.
For readability, the amdgpu_detect_virtualization was refactored into multiple individual functions.
Signed-off-by: Tony Yi <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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099bffc7 |
| 17-Feb-2025 |
Alex Deucher <[email protected]> |
drm/amdgpu: disable BAR resize on Dell G5 SE
There was a quirk added to add a workaround for a Sapphire RX 5600 XT Pulse that didn't allow BAR resizing. However, the quirk caused a regression with
drm/amdgpu: disable BAR resize on Dell G5 SE
There was a quirk added to add a workaround for a Sapphire RX 5600 XT Pulse that didn't allow BAR resizing. However, the quirk caused a regression with runtime pm on Dell laptops using those chips, rather than narrowing the scope of the resizing quirk, add a quirk to prevent amdgpu from resizing the BAR on those Dell platforms unless runtime pm is disabled.
v2: update commit message, add runpm check
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/1707 Fixes: 907830b0fc9e ("PCI: Add a REBAR size quirk for Sapphire RX 5600 XT Pulse") Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]> (cherry picked from commit 5235053f443cef4210606e5fb71f99b915a9723d) Cc: [email protected]
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5235053f |
| 17-Feb-2025 |
Alex Deucher <[email protected]> |
drm/amdgpu: disable BAR resize on Dell G5 SE
There was a quirk added to add a workaround for a Sapphire RX 5600 XT Pulse that didn't allow BAR resizing. However, the quirk caused a regression with
drm/amdgpu: disable BAR resize on Dell G5 SE
There was a quirk added to add a workaround for a Sapphire RX 5600 XT Pulse that didn't allow BAR resizing. However, the quirk caused a regression with runtime pm on Dell laptops using those chips, rather than narrowing the scope of the resizing quirk, add a quirk to prevent amdgpu from resizing the BAR on those Dell platforms unless runtime pm is disabled.
v2: update commit message, add runpm check
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/1707 Fixes: 907830b0fc9e ("PCI: Add a REBAR size quirk for Sapphire RX 5600 XT Pulse") Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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2d0f5001 |
| 16-Dec-2024 |
Thomas Weißschuh <[email protected]> |
drm/amdgpu: Constify 'struct bin_attribute'
The sysfs core now allows instances of 'struct bin_attribute' to be moved into read-only memory. Make use of that to protect them against accidental or ma
drm/amdgpu: Constify 'struct bin_attribute'
The sysfs core now allows instances of 'struct bin_attribute' to be moved into read-only memory. Make use of that to protect them against accidental or malicious modifications.
Signed-off-by: Thomas Weißschuh <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Link: https://lore.kernel.org/r/20241216-sysfs-const-bin_attr-drm-v1-4-210f2b36b9bf@weissschuh.net Signed-off-by: Greg Kroah-Hartman <[email protected]>
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3521276a |
| 19-Feb-2025 |
Sunil Khatri <[email protected]> |
drm/amdgpu: update the handle ptr in get_clockgating_state
Update the *handle to amdgpu_ip_block ptr for all functions pointers of get_clockgating_state.
Signed-off-by: Sunil Khatri <sunil.khatri@a
drm/amdgpu: update the handle ptr in get_clockgating_state
Update the *handle to amdgpu_ip_block ptr for all functions pointers of get_clockgating_state.
Signed-off-by: Sunil Khatri <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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663a8776 |
| 19-Feb-2025 |
Xiang Liu <[email protected]> |
drm/amdgpu: Check aca enabled inside cper init/fini func
Move code about checking aca enabled to the cper init/fini function to make code clean.
Signed-off-by: Xiang Liu <[email protected]> Reviewe
drm/amdgpu: Check aca enabled inside cper init/fini func
Move code about checking aca enabled to the cper init/fini function to make code clean.
Signed-off-by: Xiang Liu <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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dc0297f3 |
| 14-Feb-2025 |
Srinivasan Shanmugam <[email protected]> |
drm/amdgpu: Replace Mutex with Spinlock for RLCG register access to avoid Priority Inversion in SRIOV
RLCG Register Access is a way for virtual functions to safely access GPU registers in a virtuali
drm/amdgpu: Replace Mutex with Spinlock for RLCG register access to avoid Priority Inversion in SRIOV
RLCG Register Access is a way for virtual functions to safely access GPU registers in a virtualized environment., including TLB flushes and register reads. When multiple threads or VFs try to access the same registers simultaneously, it can lead to race conditions. By using the RLCG interface, the driver can serialize access to the registers. This means that only one thread can access the registers at a time, preventing conflicts and ensuring that operations are performed correctly. Additionally, when a low-priority task holds a mutex that a high-priority task needs, ie., If a thread holding a spinlock tries to acquire a mutex, it can lead to priority inversion. register access in amdgpu_virt_rlcg_reg_rw especially in a fast code path is critical.
The call stack shows that the function amdgpu_virt_rlcg_reg_rw is being called, which attempts to acquire the mutex. This function is invoked from amdgpu_sriov_wreg, which in turn is called from gmc_v11_0_flush_gpu_tlb.
The [ BUG: Invalid wait context ] indicates that a thread is trying to acquire a mutex while it is in a context that does not allow it to sleep (like holding a spinlock).
Fixes the below:
[ 253.013423] ============================= [ 253.013434] [ BUG: Invalid wait context ] [ 253.013446] 6.12.0-amdstaging-drm-next-lol-050225 #14 Tainted: G U OE [ 253.013464] ----------------------------- [ 253.013475] kworker/0:1/10 is trying to lock: [ 253.013487] ffff9f30542e3cf8 (&adev->virt.rlcg_reg_lock){+.+.}-{3:3}, at: amdgpu_virt_rlcg_reg_rw+0xf6/0x330 [amdgpu] [ 253.013815] other info that might help us debug this: [ 253.013827] context-{4:4} [ 253.013835] 3 locks held by kworker/0:1/10: [ 253.013847] #0: ffff9f3040050f58 ((wq_completion)events){+.+.}-{0:0}, at: process_one_work+0x3f5/0x680 [ 253.013877] #1: ffffb789c008be40 ((work_completion)(&wfc.work)){+.+.}-{0:0}, at: process_one_work+0x1d6/0x680 [ 253.013905] #2: ffff9f3054281838 (&adev->gmc.invalidate_lock){+.+.}-{2:2}, at: gmc_v11_0_flush_gpu_tlb+0x198/0x4f0 [amdgpu] [ 253.014154] stack backtrace: [ 253.014164] CPU: 0 UID: 0 PID: 10 Comm: kworker/0:1 Tainted: G U OE 6.12.0-amdstaging-drm-next-lol-050225 #14 [ 253.014189] Tainted: [U]=USER, [O]=OOT_MODULE, [E]=UNSIGNED_MODULE [ 253.014203] Hardware name: Microsoft Corporation Virtual Machine/Virtual Machine, BIOS Hyper-V UEFI Release v4.1 11/18/2024 [ 253.014224] Workqueue: events work_for_cpu_fn [ 253.014241] Call Trace: [ 253.014250] <TASK> [ 253.014260] dump_stack_lvl+0x9b/0xf0 [ 253.014275] dump_stack+0x10/0x20 [ 253.014287] __lock_acquire+0xa47/0x2810 [ 253.014303] ? srso_alias_return_thunk+0x5/0xfbef5 [ 253.014321] lock_acquire+0xd1/0x300 [ 253.014333] ? amdgpu_virt_rlcg_reg_rw+0xf6/0x330 [amdgpu] [ 253.014562] ? __lock_acquire+0xa6b/0x2810 [ 253.014578] __mutex_lock+0x85/0xe20 [ 253.014591] ? amdgpu_virt_rlcg_reg_rw+0xf6/0x330 [amdgpu] [ 253.014782] ? sched_clock_noinstr+0x9/0x10 [ 253.014795] ? srso_alias_return_thunk+0x5/0xfbef5 [ 253.014808] ? local_clock_noinstr+0xe/0xc0 [ 253.014822] ? amdgpu_virt_rlcg_reg_rw+0xf6/0x330 [amdgpu] [ 253.015012] ? srso_alias_return_thunk+0x5/0xfbef5 [ 253.015029] mutex_lock_nested+0x1b/0x30 [ 253.015044] ? mutex_lock_nested+0x1b/0x30 [ 253.015057] amdgpu_virt_rlcg_reg_rw+0xf6/0x330 [amdgpu] [ 253.015249] amdgpu_sriov_wreg+0xc5/0xd0 [amdgpu] [ 253.015435] gmc_v11_0_flush_gpu_tlb+0x44b/0x4f0 [amdgpu] [ 253.015667] gfx_v11_0_hw_init+0x499/0x29c0 [amdgpu] [ 253.015901] ? __pfx_smu_v13_0_update_pcie_parameters+0x10/0x10 [amdgpu] [ 253.016159] ? srso_alias_return_thunk+0x5/0xfbef5 [ 253.016173] ? smu_hw_init+0x18d/0x300 [amdgpu] [ 253.016403] amdgpu_device_init+0x29ad/0x36a0 [amdgpu] [ 253.016614] amdgpu_driver_load_kms+0x1a/0xc0 [amdgpu] [ 253.017057] amdgpu_pci_probe+0x1c2/0x660 [amdgpu] [ 253.017493] local_pci_probe+0x4b/0xb0 [ 253.017746] work_for_cpu_fn+0x1a/0x30 [ 253.017995] process_one_work+0x21e/0x680 [ 253.018248] worker_thread+0x190/0x330 [ 253.018500] ? __pfx_worker_thread+0x10/0x10 [ 253.018746] kthread+0xe7/0x120 [ 253.018988] ? __pfx_kthread+0x10/0x10 [ 253.019231] ret_from_fork+0x3c/0x60 [ 253.019468] ? __pfx_kthread+0x10/0x10 [ 253.019701] ret_from_fork_asm+0x1a/0x30 [ 253.019939] </TASK>
v2: s/spin_trylock/spin_lock_irqsave to be safe (Christian).
Fixes: e864180ee49b ("drm/amdgpu: Add lock around VF RLCG interface") Cc: lin cao <[email protected]> Cc: Jingwen Chen <[email protected]> Cc: Victor Skvortsov <[email protected]> Cc: Zhigang Luo <[email protected]> Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Suggested-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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4d614ce8 |
| 22-Jan-2025 |
Tao Zhou <[email protected]> |
drm/amdgpu: add RAS CPER ring buffer
And initialize it, this is a pure software ring to store RAS CPER data.
v2: change ring size to 0x100000 v2: update the initialization of count_dw of cper ring,
drm/amdgpu: add RAS CPER ring buffer
And initialize it, this is a pure software ring to store RAS CPER data.
v2: change ring size to 0x100000 v2: update the initialization of count_dw of cper ring, it's dword variable v3: skip VM inv eng for cper v3: init/fini when aca enabled
Signed-off-by: Tao Zhou <[email protected]> Signed-off-by: Xiang Liu <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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92d5d2a0 |
| 24-Jan-2025 |
Hawking Zhang <[email protected]> |
drm/amdgpu: Introduce funcs for populating CPER
Introduce utility functions designed to assist in populating CPER records.
v2: call cper_init/fini in device_ip_init/fini.
Signed-off-by: Hawking Zh
drm/amdgpu: Introduce funcs for populating CPER
Introduce utility functions designed to assist in populating CPER records.
v2: call cper_init/fini in device_ip_init/fini.
Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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6fe52b63 |
| 04-Feb-2025 |
André Almeida <[email protected]> |
drm/amdgpu: Use device wedged event
Use DRM's device wedged event to notify userspace that a reset had happened. For now, only use `none` method meant for telemetry capture.
In the future we might
drm/amdgpu: Use device wedged event
Use DRM's device wedged event to notify userspace that a reset had happened. For now, only use `none` method meant for telemetry capture.
In the future we might want to report a recovery method if the reset didn't succeed.
Acked-by: Shashank Sharma <[email protected]> Signed-off-by: André Almeida <[email protected]> Reviewed-by: Christian König <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Rodrigo Vivi <[email protected]>
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cc0e91a7 |
| 05-Feb-2025 |
Lijo Lazar <[email protected]> |
drm/amdgpu: Make VBIOS image read optional
Keep VBIOS image read optional for select SOCs in passthrough mode.
Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Alex Deucher <alexander.de
drm/amdgpu: Make VBIOS image read optional
Keep VBIOS image read optional for select SOCs in passthrough mode.
Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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