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/wasmtime-44.0.1/cranelift/codegen/src/isa/pulley_shared/inst/
H A Dargs.rs309 Cond::IfXeq32I32 { src1, src2 } => match i8::try_from(src2) { in encode()
310 Ok(src2) => encode::br_if_xeq32_i8(sink, src1, src2, rel), in encode()
313 Cond::IfXneq32I32 { src1, src2 } => match i8::try_from(src2) { in encode()
317 Cond::IfXslt32I32 { src1, src2 } => match i8::try_from(src2) { in encode()
325 Cond::IfXsgt32I32 { src1, src2 } => match i8::try_from(src2) { in encode()
333 Cond::IfXult32I32 { src1, src2 } => match u8::try_from(src2) { in encode()
341 Cond::IfXugt32I32 { src1, src2 } => match u8::try_from(src2) { in encode()
350 Cond::IfXeq64I32 { src1, src2 } => match i8::try_from(src2) { in encode()
351 Ok(src2) => encode::br_if_xeq64_i8(sink, src1, src2, rel), in encode()
354 Cond::IfXneq64I32 { src1, src2 } => match i8::try_from(src2) { in encode()
[all …]
/wasmtime-44.0.1/cranelift/codegen/src/isa/x64/
H A Dinst.isle1783 (rule (x64_imul $I16 src1 src2) (x64_imulw_rm src1 src2))
1784 (rule (x64_imul $I32 src1 src2) (x64_imull_rm src1 src2))
1785 (rule (x64_imul $I64 src1 src2) (x64_imulq_rm src1 src2))
1908 (rule (x64_andn $I8 src1 src2) (x64_andnl_rvm src1 src2))
2308 (rule (x64_pand src1 src2) (x64_pand_a_or_avx src1 src2))
2318 (rule (x64_por src1 src2) (x64_por_a_or_avx src1 src2))
2660 (rule (x64_vpmullq src1 src2) (x64_vpmullq_c src1 src2))
2703 (rule (x64_vpsraq src1 src2) (x64_vpsraq_g src1 src2))
2850 (rule (x64_bt $I16 src1 src2) (x64_btw_mr src1 src2))
2851 (rule (x64_bt $I32 src1 src2) (x64_btl_mr src1 src2))
[all …]
/wasmtime-44.0.1/winch/codegen/src/isa/x64/
H A Dasm.rs1757 src2: &Address, in xmm_vpaddus_rrm()
1761 let src2 = Self::to_synthetic_amode(src2, MemFlags::trusted()); in xmm_vpaddus_rrm() localVariable
1798 src2: &Address, in xmm_vpadd_rmr()
1873 src2: &Address, in xmm_vpinsr_rrm()
1877 let src2 = Self::to_synthetic_amode(src2, MemFlags::trusted()); in xmm_vpinsr_rrm() localVariable
1896 src2: Reg, in xmm_vpinsr_rrr()
1947 let src2 = Self::to_synthetic_amode(src2, MemFlags::trusted()); in xmm_vmovlhps_rrm() localVariable
2051 src2: &Address, in xmm_vaddp_rrm()
2265 src2: &Address, in xmm_vunpcklp_rrm()
2449 src2: &Address, in xmm_vandp_rrm()
[all …]
H A Dmasm.rs893 match src2 { in cmp()
905 RegImm::Reg(src2) => { in cmp()
929 src2: Reg, in float_cmp_with_set()
2091 src2: Reg, in v128_narrow()
2839 src2: Reg, in v128_min()
2891 writable!(src2), in v128_min()
2892 src2, in v128_min()
2910 src2: Reg, in v128_max()
2972 src2, in v128_max()
2973 src2, in v128_max()
[all …]
/wasmtime-44.0.1/pulley/src/
H A Dinterp.rs1737 let b = self.state[src2].get_u32(); in xmadd32()
1745 let b = self.state[src2].get_u64(); in xmadd64()
2278 self.state[dst].set_i32(a & src2); in xband32_s32()
2312 self.state[dst].set_i32(a | src2); in xbor32_s32()
2346 self.state[dst].set_i32(a ^ src2); in xbxor32_s32()
3208 let b = self.state[src2].get_f32(); in feq32()
3215 let b = self.state[src2].get_f32(); in fneq32()
3222 let b = self.state[src2].get_f32(); in flt32()
3229 let b = self.state[src2].get_f32(); in flteq32()
3236 let b = self.state[src2].get_f64(); in feq64()
[all …]
H A Dregs.rs177 pub src2: S2, field
182 pub fn new(dst: impl Into<D>, src1: impl Into<S1>, src2: impl Into<S2>) -> Self { in new()
186 src2: src2.into(), in new()
196 let src2 = self.src2.to_u8(); in to_bits() localVariable
197 (dst as u16) | ((src1 as u16) << 5) | ((src2 as u16) << 10) in to_bits()
205 src2: S2::new(((bits >> 10) & 0b11111) as u8).unwrap(), in from_bits()
215 let src2 = u8::from(self.src2); in to_bits() localVariable
216 (dst as u16) | ((src1 as u16) << 5) | ((src2 as u16) << 10) in to_bits()
224 src2: U6::new(((bits >> 10) & 0b111111) as u8).unwrap(), in from_bits()
497 for src2 in XReg::RANGE { in binary_operands()
[all …]
H A Dlib.rs270 xadd32_u8 = Xadd32U8 { dst: XReg, src1: XReg, src2: u8 };
277 xadd64_u8 = Xadd64U8 { dst: XReg, src1: XReg, src2: u8 };
291 xsub32_u8 = Xsub32U8 { dst: XReg, src1: XReg, src2: u8 };
298 xsub64_u8 = Xsub64U8 { dst: XReg, src1: XReg, src2: u8 };
305 xmul32_s8 = Xmul32S8 { dst: XReg, src1: XReg, src2: i8 };
777 feq32 = Feq32 { dst: XReg, src1: FReg, src2: FReg };
779 fneq32 = Fneq32 { dst: XReg, src1: FReg, src2: FReg };
781 flt32 = Flt32 { dst: XReg, src1: FReg, src2: FReg };
785 feq64 = Feq64 { dst: XReg, src1: FReg, src2: FReg };
787 fneq64 = Fneq64 { dst: XReg, src1: FReg, src2: FReg };
[all …]
H A Ddisas.rs241 self.src2.disas(position, disas); in disas()
255 self.src2.disas(position, disas); in disas()
/wasmtime-44.0.1/cranelift/codegen/meta/src/
H A Dpulley.rs45 src2: &'a str,
68 let src2 = parts.next().unwrap_or(dst); in operands() localVariable
69 Operand::Binop { dst, src1, src2 } in operands()
152 Operand::Binop { src2, .. } => { in generate_rust()
157 if src2.contains("Reg") { in generate_rust()
218 Operand::Binop { src2, .. } => { in generate_rust()
222 if src2.contains("Reg") { in generate_rust()
330 Operand::Binop { dst, src1, src2 } => { in generate_isle()
367 Operand::Binop { dst, src1, src2 } => { in generate_isle()
/wasmtime-44.0.1/pulley/tests/all/
H A Dinterp.rs150 src2: x(2), in xadd32()
170 src2: x(2), in xadd64()
195 src2: x(2), in xeq64()
220 src2: x(2), in xneq64()
252 src2: x(2), in xslt64()
284 src2: x(2), in xslteq64()
313 src2: x(2), in xult64()
342 src2: x(2), in xulteq64()
371 src2: x(2), in xeq32()
397 src2: x(2), in xneq32()
[all …]
H A Ddisas.rs47 src2: XReg::x1, in simple()
73 src2: XReg::x1, in no_offsets()
104 src2: XReg::x1, in no_offsets_or_hexdump()
/wasmtime-44.0.1/cranelift/codegen/src/isa/pulley_shared/
H A Dinst.isle116 (IfXeq32 (src1 XReg) (src2 XReg))
117 (IfXneq32 (src1 XReg) (src2 XReg))
118 (IfXslt32 (src1 XReg) (src2 XReg))
119 (IfXslteq32 (src1 XReg) (src2 XReg))
120 (IfXult32 (src1 XReg) (src2 XReg))
123 (IfXeq32I32 (src1 XReg) (src2 i32))
135 (IfXeq64 (src1 XReg) (src2 XReg))
136 (IfXneq64 (src1 XReg) (src2 XReg))
137 (IfXslt64 (src1 XReg) (src2 XReg))
139 (IfXult64 (src1 XReg) (src2 XReg))
[all …]
H A Dlower.isle1388 (rule (emit_cond (Cond.IfXeq32 src1 src2)) (pulley_xeq32 src1 src2))
1389 (rule (emit_cond (Cond.IfXneq32 src1 src2)) (pulley_xneq32 src1 src2))
1390 (rule (emit_cond (Cond.IfXslt32 src1 src2)) (pulley_xslt32 src1 src2))
1391 (rule (emit_cond (Cond.IfXslteq32 src1 src2)) (pulley_xslteq32 src1 src2))
1392 (rule (emit_cond (Cond.IfXult32 src1 src2)) (pulley_xult32 src1 src2))
1393 (rule (emit_cond (Cond.IfXulteq32 src1 src2)) (pulley_xulteq32 src1 src2))
1394 (rule (emit_cond (Cond.IfXeq64 src1 src2)) (pulley_xeq64 src1 src2))
1395 (rule (emit_cond (Cond.IfXneq64 src1 src2)) (pulley_xneq64 src1 src2))
1396 (rule (emit_cond (Cond.IfXslt64 src1 src2)) (pulley_xslt64 src1 src2))
1397 (rule (emit_cond (Cond.IfXslteq64 src1 src2)) (pulley_xslteq64 src1 src2))
[all …]
/wasmtime-44.0.1/cranelift/codegen/src/isa/s390x/
H A Dinst.isle2208 (rule (smul_wide src1 src2)
2215 (rule (umul_wide src1 src2)
4613 (rule (atomic_cas_impl $I32 src1 src2 mem) (atomic_cas32 src1 src2 mem))
4614 (rule (atomic_cas_impl $I64 src1 src2 mem) (atomic_cas64 src1 src2 mem))
4980 (rule (icmps_reg ty src1 src2) (cmp_rr (cmpop_cmps ty) src1 src2))
4983 (rule (icmps_reg_sext32 ty src1 src2) (cmp_rr (cmpop_cmps_sext32 ty) src1 src2))
5015 (rule (icmpu_reg ty src1 src2) (cmp_rr (cmpop_cmpu ty) src1 src2))
5018 (rule (icmpu_reg_zext32 ty src1 src2) (cmp_rr (cmpop_cmpu_zext32 ty) src1 src2))
5078 (rule (fcmp_reg $F32 src1 src2) (fpu_cmp32 src1 src2))
5079 (rule (fcmp_reg $F64 src1 src2) (fpu_cmp64 src1 src2))
[all …]
/wasmtime-44.0.1/cranelift/isle/veri/veri_engine/examples/store/
H A Dbroken_bvsub_store_with_load.isle99 src2))
104 (x64_add_mem ty (to_amode flags addr offset) src2))))
H A Dbroken_isub_store_with_load.isle99 src2))
104 (x64_add_mem ty (to_amode flags addr offset) src2))))
/wasmtime-44.0.1/cranelift/isle/veri/veri_engine/examples/broken/iadd/
H A Dbroken_add_extend.isle58 ;; (let ((src2 Reg (put_extended_in_reg extended_reg))
60 ;; (alu_rrr_extend op ty src1 src2 extend)))
/wasmtime-44.0.1/winch/codegen/src/
H A Dmasm.rs1772 fn cmp(&mut self, src1: Reg, src2: RegImm, size: OperandSize) -> Result<()>; in cmp()
1794 src2: Reg, in float_cmp_with_set()
2170 fn v128_and(&mut self, src1: Reg, src2: Reg, dst: WritableReg) -> Result<()>; in v128_and()
2176 fn v128_and_not(&mut self, src1: Reg, src2: Reg, dst: WritableReg) -> Result<()>; in v128_and_not()
2180 fn v128_or(&mut self, src1: Reg, src2: Reg, dst: WritableReg) -> Result<()>; in v128_or()
2184 fn v128_xor(&mut self, src1: Reg, src2: Reg, dst: WritableReg) -> Result<()>; in v128_xor()
2190 fn v128_bitselect(&mut self, src1: Reg, src2: Reg, mask: Reg, dst: WritableReg) -> Result<()>; in v128_bitselect()
2203 src2: Reg, in v128_narrow()
2281 fn v128_min(&mut self, src1: Reg, src2: Reg, dst: WritableReg, kind: V128MinKind) in v128_min()
2285 fn v128_max(&mut self, src1: Reg, src2: Reg, dst: WritableReg, kind: V128MaxKind) in v128_max()
H A Dvisitor.rs900 &mut |masm: &mut M, dst, src1, src2, size| { in visit_f32_eq()
910 &mut |masm: &mut M, dst, src1, src2, size| { in visit_f64_eq()
920 &mut |masm: &mut M, dst, src1, src2, size| { in visit_f32_ne()
930 &mut |masm: &mut M, dst, src1, src2, size| { in visit_f64_ne()
940 &mut |masm: &mut M, dst, src1, src2, size| { in visit_f32_lt()
950 &mut |masm: &mut M, dst, src1, src2, size| { in visit_f64_lt()
960 &mut |masm: &mut M, dst, src1, src2, size| { in visit_f32_gt()
970 &mut |masm: &mut M, dst, src1, src2, size| { in visit_f64_gt()
980 &mut |masm: &mut M, dst, src1, src2, size| { in visit_f32_le()
990 &mut |masm: &mut M, dst, src1, src2, size| { in visit_f64_le()
[all …]
/wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/
H A Dinst.isle2128 (rule (alu_rrr op ty src1 src2)
2251 src1 src2 shift)))
2260 src1 src2 shift)))
2341 (rule (cmn_imm size src1 src2)
2344 src1 src2)))
2351 (rule (cmp size src1 src2)
2354 src1 src2)))
2360 (rule (cmp_imm size src1 src2)
2363 src1 src2)))
2366 (rule (cmp64_imm src1 src2)
[all …]
/wasmtime-44.0.1/winch/codegen/src/isa/aarch64/
H A Dmasm.rs1053 fn cmp(&mut self, src1: Reg, src2: RegImm, size: OperandSize) -> Result<()> { in cmp()
1054 match src2 { in cmp()
1055 RegImm::Reg(src2) => { in cmp()
1056 self.asm.subs_rrr(src2, src1, size); in cmp()
1079 src2: Reg, in float_cmp_with_set()
1083 self.asm.fcmp(src1, src2, size); in float_cmp_with_set()
/wasmtime-44.0.1/winch/codegen/src/codegen/
H A Dcontext.rs374 let src2 = self.pop_to_reg(masm, None)?; in float_cmp_op() localVariable
377 emit(masm, dst, src1.reg, src2.reg, size)?; in float_cmp_op()
379 self.free_reg(src2); in float_cmp_op()
/wasmtime-44.0.1/cranelift/assembler-x64/src/
H A Dcustom.rs673 src2: &mut Fixed<R::ReadGpr, { gpr::enc::RDX }>,
684 let enc = src2.expected_enc();
685 visitor.fixed_read_gpr(&mut src2.0, enc);
/wasmtime-44.0.1/cranelift/codegen/src/isa/x64/lower/
H A Disle.rs1120 fn x64_mulxl_rvm_hi(&mut self, src1: &GprMem, src2: Gpr) -> Gpr { in x64_mulxl_rvm_hi()
1123 let inst = asm::inst::mulxl_rvm::new(ret, ret, src1, src2); in x64_mulxl_rvm_hi()
1128 fn x64_mulxq_rvm_hi(&mut self, src1: &GprMem, src2: Gpr) -> Gpr { in x64_mulxq_rvm_hi()
1131 let inst = asm::inst::mulxq_rvm::new(ret, ret, src1, src2); in x64_mulxq_rvm_hi()
/wasmtime-44.0.1/cranelift/codegen/src/isa/x64/inst/
H A Dmod.rs239 pub(crate) fn cmp_mi_sxb(size: OperandSize, src1: Gpr, src2: i8) -> Inst { in cmp_mi_sxb()
241 OperandSize::Size8 => asm::inst::cmpb_mi::new(src1, src2.cast_unsigned()).into(), in cmp_mi_sxb()
242 OperandSize::Size16 => asm::inst::cmpw_mi_sxb::new(src1, src2).into(), in cmp_mi_sxb()
243 OperandSize::Size32 => asm::inst::cmpl_mi_sxb::new(src1, src2).into(), in cmp_mi_sxb()
244 OperandSize::Size64 => asm::inst::cmpq_mi_sxb::new(src1, src2).into(), in cmp_mi_sxb()

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