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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dllvm.amdgcn.image.sample.d16.dim.ll130 %tex.vec = extractvalue {half, i32} %tex, 0
131 %tex.err = extractvalue {half, i32} %tex, 1
221 %tex.vec = extractvalue {<2 x half>, i32} %tex, 0
222 %tex.err = extractvalue {<2 x half>, i32} %tex, 1
223 %tex.vecf = bitcast <2 x half> %tex.vec to float
225 %tex.errf = bitcast i32 %tex.err to float
353 %tex.vec = extractvalue {<3 x half>, i32} %tex, 0
355 %tex.err = extractvalue {<3 x half>, i32} %tex, 1
361 %tex.errf = bitcast i32 %tex.err to float
491 %tex.vec = extractvalue {<4 x half>, i32} %tex, 0
[all …]
H A Drv7x0_count3.ll15 …%tmp9 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 …
17 …%tmp11 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp10, i32 0, i32 0, i32 0, i32 1, i32 0, i3…
19 …%tmp13 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp12, i32 0, i32 0, i32 0, i32 2, i32 0, i3…
21 …%tmp15 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp14, i32 0, i32 0, i32 0, i32 3, i32 0, i3…
23 …%tmp17 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp16, i32 0, i32 0, i32 0, i32 4, i32 0, i3…
25 …%tmp19 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp18, i32 0, i32 0, i32 0, i32 5, i32 0, i3…
27 …%tmp21 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp20, i32 0, i32 0, i32 0, i32 6, i32 0, i3…
29 …%tmp23 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp22, i32 0, i32 0, i32 0, i32 7, i32 0, i3…
31 …%tmp25 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp24, i32 0, i32 0, i32 0, i32 8, i32 0, i3…
33 …%tmp27 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp26, i32 0, i32 0, i32 0, i32 9, i32 0, i3…
[all …]
H A Dfetch-limits.r700+.ll39 …%18 = call <4 x float> @llvm.r600.tex(<4 x float> %17, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i…
41 …%20 = call <4 x float> @llvm.r600.tex(<4 x float> %19, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i…
43 …%22 = call <4 x float> @llvm.r600.tex(<4 x float> %21, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i…
45 …%24 = call <4 x float> @llvm.r600.tex(<4 x float> %23, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i…
47 …%26 = call <4 x float> @llvm.r600.tex(<4 x float> %25, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i…
49 …%28 = call <4 x float> @llvm.r600.tex(<4 x float> %27, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i…
51 …%30 = call <4 x float> @llvm.r600.tex(<4 x float> %29, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i…
53 …%32 = call <4 x float> @llvm.r600.tex(<4 x float> %31, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i…
55 …%34 = call <4 x float> @llvm.r600.tex(<4 x float> %33, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i…
57 …%36 = call <4 x float> @llvm.r600.tex(<4 x float> %35, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i…
[all …]
H A Dfetch-limits.r600.ll22 …%tmp10 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp9, i32 0, i32 0, i32 0, i32 0, i32 0, i32…
24 …%tmp12 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp11, i32 0, i32 0, i32 0, i32 0, i32 0, i3…
26 …%tmp14 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp13, i32 0, i32 0, i32 0, i32 0, i32 0, i3…
28 …%tmp16 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp15, i32 0, i32 0, i32 0, i32 0, i32 0, i3…
30 …%tmp18 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp17, i32 0, i32 0, i32 0, i32 0, i32 0, i3…
32 …%tmp20 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp19, i32 0, i32 0, i32 0, i32 0, i32 0, i3…
34 …%tmp22 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp21, i32 0, i32 0, i32 0, i32 0, i32 0, i3…
36 …%tmp24 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp23, i32 0, i32 0, i32 0, i32 0, i32 0, i3…
38 …%tmp26 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp25, i32 0, i32 0, i32 0, i32 0, i32 0, i3…
54 declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) #0
H A Dllvm.r600.tex.ll24 …%tmp1 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1…
26 …%tmp3 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp2, i32 0, i32 0, i32 0, i32 0, i32 0, i32 …
28 …%tmp5 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp4, i32 0, i32 0, i32 0, i32 0, i32 0, i32 …
30 …%tmp7 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp6, i32 0, i32 0, i32 0, i32 0, i32 0, i32 …
32 …%tmp9 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 …
40 …%tmp17 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp16, i32 0, i32 0, i32 0, i32 0, i32 0, i3…
42 …%tmp19 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp18, i32 0, i32 0, i32 0, i32 0, i32 0, i3…
50 …%tmp27 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp26, i32 0, i32 0, i32 0, i32 0, i32 0, i3…
52 …%tmp29 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp28, i32 0, i32 0, i32 0, i32 0, i32 0, i3…
54 …%tmp31 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp30, i32 0, i32 0, i32 0, i32 0, i32 0, i3…
[all …]
H A Dtexture-input-merge.ll19 …%14 = call <4 x float> @llvm.r600.tex(<4 x float> %10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i…
20 …%15 = call <4 x float> @llvm.r600.tex(<4 x float> %12, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i…
21 …%16 = call <4 x float> @llvm.r600.tex(<4 x float> %13, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i…
28 declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readno…
H A Dllvm.amdgcn.image.d16.dim.ll12 …%tex = call half @llvm.amdgcn.image.load.2d.f16.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0,…
13 ret half %tex
23 …%tex = call <2 x half> @llvm.amdgcn.image.load.2d.v2f16.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc…
24 %r = bitcast <2 x half> %tex to float
34 …%tex = call <3 x half> @llvm.amdgcn.image.load.2d.v3f16.i32(i32 7, i32 %s, i32 %t, <8 x i32> %rsrc…
35 %ext = shufflevector <3 x half> %tex, <3 x half> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
47 …%tex = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i32(i32 15, i32 %s, i32 %t, <8 x i32> %rsr…
48 %r = bitcast <4 x half> %tex to <2 x float>
60 %r = bitcast <4 x half> %tex to <2 x float>
72 %x = bitcast <2 x half> %tex to float
[all …]
H A Dtex-clause-antidep.ll15 …%9 = call <4 x float> @llvm.r600.tex(<4 x float> %8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32…
16 …%10 = call <4 x float> @llvm.r600.tex(<4 x float> %8, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i3…
22 declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readno…
H A Dllvm.amdgcn.image.gather4.d16.dim.ll15 …%tex = call <4 x half> @llvm.amdgcn.image.gather4.b.2d.v4f16.f32.f32(i32 4, float %bias, float %s,…
16 %r = bitcast <4 x half> %tex to <2 x float>
H A Delse.ll45 …%tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %c, <8 x i32> undef, …
46 %v.else = extractelement <4 x float> %tex, i32 0
H A Dllvm.r600.cube.ll41 …%tmp31 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp30, i32 0, i32 0, i32 0, i32 16, i32 0, i…
55 declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) #0
H A Dwqm.ll27 ret <4 x float> %tex
68 ret <4 x float> %tex
96 %tex.1 = bitcast <4 x float> %tex to <4 x i32>
97 %tex.2 = extractelement <4 x i32> %tex.1, i32 0
144 %tex.0 = extractelement <4 x float> %tex, i32 0
145 %tex.1 = extractelement <4 x float> %tex, i32 1
146 %tex.2 = extractelement <4 x float> %tex, i32 2
147 %tex.3 = extractelement <4 x float> %tex, i32 3
148 …call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tex.0, float %tex.1, float %tex.2, float %tex…
1557 %tex.END = phi float [ %tex.IF, %IF ], [ %tex.ELSE, %ELSE ]
[all …]
H A Dvgpr-liverange-ir.ll561 %tex = type opaque
562 define protected amdgpu_kernel void @nested_waterfalls(%tex* addrspace(1)* %tex.coerce) local_unnam…
570 …lled [[COPY]](p4), 36, 0 :: (dereferenceable invariant load (s64) from %ir.tex.coerce.kernarg.offs…
665 %idx = getelementptr inbounds %tex*, %tex* addrspace(1)* %tex.coerce, i64 %1
666 %2 = load %tex*, %tex* addrspace(1)* %idx, align 8
667 %3 = bitcast %tex* %2 to i32*
670 %5 = bitcast %tex* %2 to <8 x i32>*
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Dtex-read-cuda.ll9 declare { float, float, float, float } @llvm.nvvm.tex.unified.1d.v4f32.s32(i64, i32)
16 ; SM20: tex.1d.v4.f32.s32 {%f[[RED:[0-9]+]], %f[[GREEN:[0-9]+]], %f[[BLUE:[0-9]+]], %f[[ALPHA:[0-9]…
18 ; SM30: tex.1d.v4.f32.s32 {%f[[RED:[0-9]+]], %f[[GREEN:[0-9]+]], %f[[BLUE:[0-9]+]], %f[[ALPHA:[0-9]…
19 …%val = tail call { float, float, float, float } @llvm.nvvm.tex.unified.1d.v4f32.s32(i64 %img, i32 …
35 ; SM20: tex.1d.v4.f32.s32 {%f[[RED:[0-9]+]], %f[[GREEN:[0-9]+]], %f[[BLUE:[0-9]+]], %f[[ALPHA:[0-9]…
36 ; SM30: tex.1d.v4.f32.s32 {%f[[RED:[0-9]+]], %f[[GREEN:[0-9]+]], %f[[BLUE:[0-9]+]], %f[[ALPHA:[0-9]…
37 …%val = tail call { float, float, float, float } @llvm.nvvm.tex.unified.1d.v4f32.s32(i64 %texHandle…
52 ; SM20: tex.1d.v4.f32.s32 {%f[[RED:[0-9]+]], %f[[GREEN:[0-9]+]], %f[[BLUE:[0-9]+]], %f[[ALPHA:[0-9]…
53 ; SM30: tex.1d.v4.f32.s32 {%f[[RED:[0-9]+]], %f[[GREEN:[0-9]+]], %f[[BLUE:[0-9]+]], %f[[ALPHA:[0-9]…
54 …%val = tail call { float, float, float, float } @llvm.nvvm.tex.unified.1d.v4f32.s32(i64 %texHandle…
H A Dtex-read.ll6 declare { float, float, float, float } @llvm.nvvm.tex.1d.v4f32.s32(i64, i64, i32)
10 ; CHECK: tex.1d.v4.f32.s32 {%f[[RED:[0-9]+]], %f[[GREEN:[0-9]+]], %f[[BLUE:[0-9]+]], %f[[ALPHA:[0-9…
11 …%val = tail call { float, float, float, float } @llvm.nvvm.tex.1d.v4f32.s32(i64 %img, i64 %sampler…
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DIntrinsicsNVVM.td1737 "llvm.nvvm.tex.1d.v4f32.s32">;
1741 "llvm.nvvm.tex.1d.v4f32.f32">;
1754 "llvm.nvvm.tex.1d.v4s32.s32">;
1758 "llvm.nvvm.tex.1d.v4s32.f32">;
1771 "llvm.nvvm.tex.1d.v4u32.s32">;
1775 "llvm.nvvm.tex.1d.v4u32.f32">;
1844 "llvm.nvvm.tex.2d.v4f32.s32">;
1848 "llvm.nvvm.tex.2d.v4f32.f32">;
1862 "llvm.nvvm.tex.2d.v4s32.s32">;
1866 "llvm.nvvm.tex.2d.v4s32.f32">;
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-llvm.amdgcn.image.load.2d.ll25 ret float %tex
51 ret <2 x float> %tex
78 ret <3 x float> %tex
106 ret <4 x float> %tex
136 ret float %tex
167 ret <2 x float> %tex
199 ret <3 x float> %tex
232 ret <4 x float> %tex
246 ret float %tex
272 ret <2 x float> %tex
[all …]
H A Dlegalize-llvm.amdgcn.image.load.2d.d16.ll47 ret half %tex
98 ret <2 x half> %tex
172 ret <3 x half> %tex
231 ret <4 x half> %tex
283 ret half %tex
343 ret <2 x half> %tex
426 ret <3 x half> %tex
494 ret <4 x half> %tex
517 ret half %tex
567 ret <2 x half> %tex
[all …]
H A Dlegalize-llvm.amdgcn.image.load.3d.ll46 …%tex = call float @llvm.amdgcn.image.load.3d.f32.i32(i32 1, i32 %s, i32 %t, i32 %r, <8 x i32> %rsr…
47 ret float %tex
97 %tex = extractvalue { float, i32 } %val, 0
100 ret float %tex
/llvm-project-15.0.7/clang/test/CodeGenCUDA/
H A Dtexture.cu32 texture<float, 2, ElementType> tex; variable
48 return tex2d_ld(tex, x, y).x + tex2d_ld(norm, int(x), int(y)).x; in foo()
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXIntrinsics.td3231 : TEX_CUBE_ARRAY_LEVEL<"tex.level.acube.v4.f32.f32",
3234 : TEX_CUBE_ARRAY_LEVEL<"tex.level.acube.v4.s32.f32",
3237 : TEX_CUBE_ARRAY_LEVEL<"tex.level.acube.v4.u32.f32",
3294 NVPTXRegClass intype, dag tex>
3297 !con(tex, (ins intype:$x)),
3448 !con(tex, (ins intype:$x, intype:$y)),
3496 !con(tex, (ins intype:$x, intype:$y,
3705 : TEX_UNIFIED_CUBE_LEVEL<"tex.level.cube.v4.f32.f32",
3708 : TEX_UNIFIED_CUBE_LEVEL<"tex.level.cube.v4.s32.f32",
3711 : TEX_UNIFIED_CUBE_LEVEL<"tex.level.cube.v4.u32.f32",
[all …]
/llvm-project-15.0.7/libclc/r600/lib/image/
H A Dread_image_impl.ll5 declare <4 x float> @llvm.R600.tex(<4 x float>, i32, i32, i32, i32, i32, i32,
35 %data.norm = call <4 x float> @llvm.R600.tex(
42 %data.unnorm = call <4 x float> @llvm.R600.tex(
/llvm-project-15.0.7/clang/test/SemaCUDA/
H A Dconstexpr-var.cu85 texture<float, 2, ElementType> tex; variable
102 __device__ static constexpr texture<float, 2, ElementType> *const p6 = &tex;
H A Dconst-var.cu84 texture<float, 2, ElementType> tex; variable
109 __device__ texture<float, 2, ElementType> *const B::p6 = &tex;
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/AMDGPU/
H A Dimage-d16.ll20 …%tex = call float @llvm.amdgcn.image.sample.lz.2d.f32.f32(i32 1, float %s, float %t, <8 x i32> %rs…
21 %tex_half = fptrunc float %tex to half
44 …%tex = call <2 x float> @llvm.amdgcn.image.sample.lz.2d.v2f32.f32(i32 3, float %s, float %t, <8 x …
45 %tex_2_half = fptrunc <2 x float> %tex to <2 x half>
75 …%tex = call <3 x float> @llvm.amdgcn.image.sample.lz.2d.v3f32.f32(i32 7, float %s, float %t, <8 x …
76 %tex_3_half = fptrunc <3 x float> %tex to <3 x half>
112 …%tex = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32(i32 15, float %s, float %t, <8 x…
113 %tex_4_half = fptrunc <4 x float> %tex to <4 x half>
151 …%tex = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f16(i32 1, half %s, half %t, <8 x i32>…
152 %tex_4_half = fptrunc <4 x float> %tex to <4 x half>

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