1; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s
2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
3
4; CHECK-LABEL: {{^}}else_no_execfix:
5; CHECK: ; %Flow
6; CHECK-NEXT: s_andn2_saveexec_b64 [[DST:s\[[0-9]+:[0-9]+\]]], [[DST]]
7define amdgpu_ps float @else_no_execfix(i32 %z, float %v) #0 {
8main_body:
9  %cc = icmp sgt i32 %z, 5
10  br i1 %cc, label %if, label %else
11
12if:
13  %v.if = fmul float %v, 2.0
14  br label %end
15
16else:
17  %v.else = fmul float %v, 3.0
18  br label %end
19
20end:
21  %r = phi float [ %v.if, %if ], [ %v.else, %else ]
22  ret float %r
23}
24
25; CHECK-LABEL: {{^}}else_execfix_leave_wqm:
26; CHECK: ; %bb.0:
27; CHECK-NEXT: s_mov_b64 [[INIT_EXEC:s\[[0-9]+:[0-9]+\]]], exec
28; CHECK: ; %Flow
29; CHECK-NEXT: s_or_saveexec_b64 [[DST:s\[[0-9]+:[0-9]+\]]],
30; CHECK-NEXT: s_and_b64 exec, exec, [[INIT_EXEC]]
31; CHECK-NEXT: s_and_b64 [[AND_INIT:s\[[0-9]+:[0-9]+\]]], exec, [[DST]]
32; CHECK-NEXT: s_xor_b64 exec, exec, [[AND_INIT]]
33; CHECK-NEXT: s_cbranch_execz
34define amdgpu_ps void @else_execfix_leave_wqm(i32 %z, float %v) #0 {
35main_body:
36  %cc = icmp sgt i32 %z, 5
37  br i1 %cc, label %if, label %else
38
39if:
40  %v.if = fmul float %v, 2.0
41  br label %end
42
43else:
44  %c = fmul float %v, 3.0
45  %tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %c, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
46  %v.else = extractelement <4 x float> %tex, i32 0
47  br label %end
48
49end:
50  %r = phi float [ %v.if, %if ], [ %v.else, %else ]
51  call void @llvm.amdgcn.raw.buffer.store.f32(float %r, <4 x i32> undef, i32 0, i32 0, i32 0)
52  ret void
53}
54
55declare void @llvm.amdgcn.raw.buffer.store.f32(float, <4 x i32>, i32, i32, i32 immarg) #1
56declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 immarg, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #2
57
58attributes #0 = { nounwind }
59attributes #1 = { nounwind writeonly }
60attributes #2 = { nounwind readonly }
61