| /llvm-project-15.0.7/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 105 setTargetDAGCombine(ISD::AND); in LoongArchTargetLowering()
106 setTargetDAGCombine(ISD::OR); in LoongArchTargetLowering()
107 setTargetDAGCombine(ISD::SRL); in LoongArchTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 161 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); in WebAssemblyTargetLowering()
164 setTargetDAGCombine({ISD::SIGN_EXTEND, ISD::ZERO_EXTEND}); in WebAssemblyTargetLowering()
168 setTargetDAGCombine({ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_EXTEND, in WebAssemblyTargetLowering()
173 setTargetDAGCombine({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, in WebAssemblyTargetLowering()
176 setTargetDAGCombine(ISD::TRUNCATE); in WebAssemblyTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 941 setTargetDAGCombine({ISD::INTRINSIC_WO_CHAIN, ISD::ADD, ISD::SUB, ISD::AND, in RISCVTargetLowering()
944 setTargetDAGCombine(ISD::SRA); in RISCVTargetLowering()
947 setTargetDAGCombine({ISD::FADD, ISD::FMAXNUM, ISD::FMINNUM}); in RISCVTargetLowering()
950 setTargetDAGCombine({ISD::ROTL, ISD::ROTR}); in RISCVTargetLowering()
953 setTargetDAGCombine({ISD::UMAX, ISD::UMIN, ISD::SMAX, ISD::SMIN}); in RISCVTargetLowering()
956 setTargetDAGCombine(ISD::BITREVERSE); in RISCVTargetLowering()
958 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG); in RISCVTargetLowering()
960 setTargetDAGCombine({ISD::ZERO_EXTEND, ISD::FP_TO_SINT, ISD::FP_TO_UINT, in RISCVTargetLowering()
963 setTargetDAGCombine({ISD::FCOPYSIGN, ISD::MGATHER, ISD::MSCATTER, in RISCVTargetLowering()
967 setTargetDAGCombine(ISD::BITCAST); in RISCVTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 102 setTargetDAGCombine( in MipsSETargetLowering()
161 setTargetDAGCombine({ISD::AND, ISD::OR, ISD::SRA, ISD::VSELECT, ISD::XOR}); in MipsSETargetLowering()
204 setTargetDAGCombine(ISD::MUL); in MipsSETargetLowering()
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| H A D | MipsISelLowering.cpp | 483 setTargetDAGCombine({ISD::SDIVREM, ISD::UDIVREM, ISD::SELECT, ISD::AND, in MipsTargetLowering()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 869 setTargetDAGCombine(ISD::OR); in AArch64TargetLowering()
871 setTargetDAGCombine(ISD::AND); in AArch64TargetLowering()
882 setTargetDAGCombine(ISD::SETCC); in AArch64TargetLowering()
884 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); in AArch64TargetLowering()
891 setTargetDAGCombine(ISD::LOAD); in AArch64TargetLowering()
893 setTargetDAGCombine(ISD::MSTORE); in AArch64TargetLowering()
895 setTargetDAGCombine(ISD::MUL); in AArch64TargetLowering()
897 setTargetDAGCombine({ISD::SELECT, ISD::VSELECT}); in AArch64TargetLowering()
903 setTargetDAGCombine({ISD::MGATHER, ISD::MSCATTER}); in AArch64TargetLowering()
905 setTargetDAGCombine(ISD::FP_EXTEND); in AArch64TargetLowering()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 141 setTargetDAGCombine({ISD::ADD, ISD::SUB, ISD::AND, ISD::OR, ISD::XOR}); in LanaiTargetLowering()
|
| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 1361 setTargetDAGCombine({ISD::ADD, ISD::SHL, ISD::SRA, ISD::SRL, ISD::MUL, in PPCTargetLowering()
1364 setTargetDAGCombine(ISD::UINT_TO_FP); in PPCTargetLowering()
1365 setTargetDAGCombine({ISD::LOAD, ISD::STORE, ISD::BR_CC}); in PPCTargetLowering()
1367 setTargetDAGCombine(ISD::BRCOND); in PPCTargetLowering()
1368 setTargetDAGCombine({ISD::BSWAP, ISD::INTRINSIC_WO_CHAIN, in PPCTargetLowering()
1371 setTargetDAGCombine({ISD::SIGN_EXTEND, ISD::ZERO_EXTEND, ISD::ANY_EXTEND}); in PPCTargetLowering()
1373 setTargetDAGCombine({ISD::TRUNCATE, ISD::VECTOR_SHUFFLE}); in PPCTargetLowering()
1376 setTargetDAGCombine({ISD::TRUNCATE, ISD::SETCC, ISD::SELECT_CC}); in PPCTargetLowering()
1380 setTargetDAGCombine({ISD::ABS, ISD::VSELECT}); in PPCTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 825 setTargetDAGCombine({ISD::BRCOND, ISD::BR_CC}); in ARMTargetLowering()
997 setTargetDAGCombine({ISD::SHL, ISD::SRL, ISD::SRA, ISD::FP_TO_SINT, in ARMTargetLowering()
1012 setTargetDAGCombine( in ARMTargetLowering()
1020 setTargetDAGCombine({ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX, in ARMTargetLowering()
1025 setTargetDAGCombine(ISD::FADD); in ARMTargetLowering()
1564 setTargetDAGCombine( in ARMTargetLowering()
1568 setTargetDAGCombine(ISD::VSELECT); in ARMTargetLowering()
1571 setTargetDAGCombine(ISD::SRL); in ARMTargetLowering()
1573 setTargetDAGCombine(ISD::SHL); in ARMTargetLowering()
1577 setTargetDAGCombine({ISD::SMIN, ISD::SMAX}); in ARMTargetLowering()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 547 setTargetDAGCombine({ISD::ADD, ISD::AND, ISD::FADD, ISD::MUL, ISD::SHL, in NVPTXTargetLowering()
553 setTargetDAGCombine(ISD::SETCC); in NVPTXTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 199 setTargetDAGCombine({ISD::FP_ROUND, ISD::FP_TO_SINT, ISD::EXTRACT_VECTOR_ELT, in R600TargetLowering()
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| H A D | AMDGPUISelLowering.cpp | 468 setTargetDAGCombine({ISD::BITCAST, ISD::SHL, in AMDGPUTargetLowering()
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| H A D | SIISelLowering.cpp | 720 setTargetDAGCombine({ISD::ADD, in SITargetLowering()
750 setTargetDAGCombine({ISD::LOAD, in SITargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 170 setTargetDAGCombine( in XCoreTargetLowering()
|
| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 2442 void setTargetDAGCombine(ArrayRef<ISD::NodeType> NTs) { in setTargetDAGCombine() function
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| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 906 setTargetDAGCombine(ISD::TRUNCATE); in VETargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 389 setTargetDAGCombine({ISD::SPLAT_VECTOR, ISD::VSELECT}); in initializeHVXLowering()
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| H A D | HexagonISelLowering.cpp | 1812 setTargetDAGCombine(ISD::VSELECT); in HexagonTargetLowering()
|
| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1911 setTargetDAGCombine(ISD::BITCAST); in SparcTargetLowering()
|
| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 646 setTargetDAGCombine({ISD::ZERO_EXTEND, in SystemZTargetLowering()
|
| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 2325 setTargetDAGCombine({ISD::VECTOR_SHUFFLE, in X86TargetLowering()
|