Home
last modified time | relevance | path

Searched refs:setDesc (Results 1 – 25 of 102) sorted by relevance

12345

/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyLowerBrUnless.cpp80 Def->setDesc(TII.get(NE_I32)); in runOnMachineFunction()
84 Def->setDesc(TII.get(EQ_I32)); in runOnMachineFunction()
88 Def->setDesc(TII.get(LE_S_I32)); in runOnMachineFunction()
92 Def->setDesc(TII.get(LT_S_I32)); in runOnMachineFunction()
96 Def->setDesc(TII.get(GE_S_I32)); in runOnMachineFunction()
120 Def->setDesc(TII.get(NE_I64)); in runOnMachineFunction()
124 Def->setDesc(TII.get(EQ_I64)); in runOnMachineFunction()
160 Def->setDesc(TII.get(NE_F32)); in runOnMachineFunction()
164 Def->setDesc(TII.get(EQ_F32)); in runOnMachineFunction()
168 Def->setDesc(TII.get(NE_F64)); in runOnMachineFunction()
[all …]
H A DWebAssemblyRegStackify.cpp107 MI->setDesc(TII->get(WebAssembly::CONST_I32)); in convertImplicitDefToConstZero()
110 MI->setDesc(TII->get(WebAssembly::CONST_I64)); in convertImplicitDefToConstZero()
113 MI->setDesc(TII->get(WebAssembly::CONST_F32)); in convertImplicitDefToConstZero()
118 MI->setDesc(TII->get(WebAssembly::CONST_F64)); in convertImplicitDefToConstZero()
123 MI->setDesc(TII->get(WebAssembly::CONST_V128_I64x2)); in convertImplicitDefToConstZero()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp256 MIB->setDesc(TII.get(ARM::VMOVDRR)); in selectMergeValues()
288 MIB->setDesc(TII.get(ARM::VMOVRRD)); in selectUnmergeValues()
677 MIB->setDesc(TII.get(Opc)); in selectGlobal()
715 MIB->setDesc(TII.get(Opc)); in selectGlobal()
807 MIB->setDesc(TII.get(ARM::MOVsr)); in selectShift()
902 I.setDesc(TII.get(NewOpc)); in select()
958 I.setDesc(TII.get(COPY)); in select()
984 I.setDesc(TII.get(ARM::MOVi)); in select()
1030 I.setDesc(TII.get(COPY)); in select()
1099 I.setDesc(TII.get(NewOpc)); in select()
[all …]
H A DThumb2InstrInfo.cpp555 MI.setDesc(TII.get(ARM::tMOVr)); in rewriteT2FrameIndex()
570 MI.setDesc(IsSP ? TII.get(ARM::t2SUBspImm) : TII.get(ARM::t2SUBri)); in rewriteT2FrameIndex()
572 MI.setDesc(IsSP ? TII.get(ARM::t2ADDspImm) : TII.get(ARM::t2ADDri)); in rewriteT2FrameIndex()
590 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
710 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
754 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc))); in rewriteT2FrameIndex()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZShortenInst.cpp96 MI.setDesc(TII->get(LLIxL)); in shortenIIF()
101 MI.setDesc(TII->get(LLIxH)); in shortenIIF()
112 MI.setDesc(TII->get(Opcode)); in shortenOn0()
123 MI.setDesc(TII->get(Opcode)); in shortenOn01()
136 MI.setDesc(TII->get(Opcode)); in shortenOn001()
169 MI.setDesc(TII->get(Opcode)); in shortenFPConv()
196 MI.setDesc(TII->get(Opcode)); in shortenFusedFPOp()
365 MI.setDesc(TII->get(TwoOperandOpcode)); in processBlock()
H A DSystemZPostRewrite.cpp88 MBBI->setDesc(TII->get(LowOpcode)); in selectLOCRMux()
90 MBBI->setDesc(TII->get(HighOpcode)); in selectLOCRMux()
139 MBBI->setDesc(TII->get(LowOpcode)); in selectSELRMux()
141 MBBI->setDesc(TII->get(HighOpcode)); in selectSELRMux()
216 MI.setDesc(TII->get(TargetMemOpcode)); in selectMI()
H A DSystemZInstrInfo.cpp114 EarlierMI->setDesc(get(HighOpcode)); in splitMove()
115 MI->setDesc(get(LowOpcode)); in splitMove()
132 MI->setDesc(get(NewOpcode)); in splitAdjDynAlloc()
164 MI.setDesc(get(LowOpcodeK)); in expandRIEPseudo()
186 MI.setDesc(get(Opcode)); in expandRXYPseudo()
196 MI.setDesc(get(Opcode)); in expandLOCPseudo()
241 MI->setDesc(get(SystemZ::LG)); in expandLoadStackGuard()
667 UseMI.setDesc(get(NewUseOpc)); in FoldImmediate()
732 MI.setDesc(get(SystemZ::CondTrap)); in PredicateInstruction()
752 MI.setDesc(get(SystemZ::CallBRCL)); in PredicateInstruction()
[all …]
H A DSystemZElimCompare.cpp228 Branch->setDesc(TII->get(BRCT)); in convertToBRCT()
271 Branch->setDesc(TII->get(LATOpcode)); in convertToLoadAndTrap()
331 MI.setDesc(TII->get(ConvOpc)); in convertToLogical()
669 Branch->setDesc(TII->get(FusedOpcode)); in fuseCompareOperations()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DExpandPostRAPseudos.cpp104 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
117 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
144 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
161 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIOptimizeExecMasking.cpp214 MI.setDesc(TII->get(RegSrc ? AMDGPU::COPY : AMDGPU::S_MOV_B32)); in removeTerminatorBit()
219 MI.setDesc(TII->get(RegSrc ? AMDGPU::COPY : AMDGPU::S_MOV_B64)); in removeTerminatorBit()
225 MI.setDesc(TII->get(AMDGPU::S_XOR_B64)); in removeTerminatorBit()
231 MI.setDesc(TII->get(AMDGPU::S_XOR_B32)); in removeTerminatorBit()
237 MI.setDesc(TII->get(AMDGPU::S_OR_B64)); in removeTerminatorBit()
243 MI.setDesc(TII->get(AMDGPU::S_OR_B32)); in removeTerminatorBit()
249 MI.setDesc(TII->get(AMDGPU::S_ANDN2_B64)); in removeTerminatorBit()
255 MI.setDesc(TII->get(AMDGPU::S_ANDN2_B32)); in removeTerminatorBit()
261 MI.setDesc(TII->get(AMDGPU::S_AND_B64)); in removeTerminatorBit()
267 MI.setDesc(TII->get(AMDGPU::S_AND_B32)); in removeTerminatorBit()
H A DSIShrinkInstructions.cpp224 MI.setDesc(TII->get(SOPKOpc)); in shrinkScalarCompare()
234 MI.setDesc(NewDesc); in shrinkScalarCompare()
332 MI.setDesc(TII->get(NewOpcode)); in shrinkMIMG()
431 MI.setDesc(TII->get(NewOpcode)); in shrinkMadFma()
490 MI.setDesc(TII->get(Opc)); in shrinkScalarLogicOp()
762 MI.setDesc(TII->get(AMDGPU::V_BFREV_B32_e32)); in runOnMachineFunction()
803 MI.setDesc(TII->get(Opc)); in runOnMachineFunction()
823 MI.setDesc(TII->get(AMDGPU::S_MOVK_I32)); in runOnMachineFunction()
825 MI.setDesc(TII->get(AMDGPU::S_BREV_B32)); in runOnMachineFunction()
H A DSIFoldOperands.cpp271 MI->setDesc(TII.get(AMDGPU::IMPLICIT_DEF)); in updateOperand()
285 MI->setDesc(TII.get(NewMFMAOpc)); in updateOperand()
342 MI->setDesc(TII->get(NewOpc)); in tryAddToFoldList()
348 MI->setDesc(TII->get(Opc)); in tryAddToFoldList()
359 MI->setDesc(TII->get(ImmOpc)); in tryAddToFoldList()
662 UseMI->setDesc(TII->get(NewOpc)); in foldOperand()
718 UseMI->setDesc(TII->get(MovOp)); in foldOperand()
751 UseMI->setDesc(TII->get(AMDGPU::REG_SEQUENCE)); in foldOperand()
850 UseMI->setDesc(TII->get(AMDGPU::S_MOV_B32)); in foldOperand()
871 UseMI->setDesc(TII->get(AMDGPU::COPY)); in foldOperand()
[all …]
H A DSIPreEmitPeephole.cpp196 MI.setDesc(TII->get(AMDGPU::S_BRANCH)); in optimizeVccBranch()
224 MI.setDesc(TII->get(AMDGPU::S_BRANCH)); in optimizeVccBranch()
234 MI.setDesc( in optimizeVccBranch()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp307 I.setDesc(TII.get(X86::COPY)); in selectCopy()
539 I.setDesc(TII.get(NewOpc)); in selectLoadStoreOp()
575 I.setDesc(TII.get(NewOpc)); in selectFrameIndexOrGep()
627 I.setDesc(TII.get(NewOpc)); in selectGlobalValue()
679 I.setDesc(TII.get(NewOpc)); in selectConstant()
704 I.setDesc(TII.get(X86::COPY)); in selectTurnIntoCOPY()
770 I.setDesc(TII.get(X86::COPY)); in selectTruncOrPtrToInt()
879 I.setDesc(TII.get(X86::COPY)); in selectAnyext()
1265 I.setDesc(TII.get(X86::VINSERTF128rr)); in selectInsert()
1468 I.setDesc(TII.get(X86::IMPLICIT_DEF)); in selectImplicitDefOrPHI()
[all …]
H A DX86ExpandPseudo.cpp550 MI.setDesc(TII->get(X86::LDTILECFG)); in ExpandMI()
559 MI.setDesc(TII->get(Opc)); in ExpandMI()
579 MI.setDesc(TII->get(Opc)); in ExpandMI()
586 MI.setDesc(TII->get(X86::TILESTORED)); in ExpandMI()
592 MI.setDesc(TII->get(X86::TILEZERO)); in ExpandMI()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVERegisterInfo.cpp258 MI.setDesc(get(VE::STrii)); in processSTQ()
278 MI.setDesc(get(VE::LDrii)); in processLDQ()
317 MI.setDesc(get(VE::STrii)); in processSTVM()
353 MI.setDesc(get(VE::LDrii)); in processLDVM()
415 MI.setDesc(get(VE::STrii)); in processSTVM512()
454 MI.setDesc(get(VE::LDrii)); in processLDVM512()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64CompressJumpTables.cpp147 MI.setDesc(TII->get(AArch64::JumpTableDest8)); in compressJumpTable()
153 MI.setDesc(TII->get(AArch64::JumpTableDest16)); in compressJumpTable()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp190 slot->setDesc(Subtarget->getInstrInfo()->get(SP::RET)); in findDelayInstr()
394 AddMI->setDesc(TII->get((AddMI->getOpcode() == SP::ADDrr) in combineRestoreADD()
433 OrMI->setDesc(TII->get((OrMI->getOpcode() == SP::ORrr) in combineRestoreOR()
470 RestoreMI->setDesc(TII->get(SP::RESTOREri)); in combineRestoreSETHIi()
H A DSparcRegisterInfo.cpp192 MI.setDesc(TII.get(SP::STDFri)); in eliminateFrameIndex()
205 MI.setDesc(TII.get(SP::LDDFri)); in eliminateFrameIndex()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCEarlyReturn.cpp93 MI->setDesc(TII->get(PPC::BCCLR)); in processBlock()
110 MI->setDesc( in processBlock()
H A DPPCInstrInfo.cpp2197 MI.setDesc(get(PPC::BCLR)); in PredicateInstruction()
2223 MI.setDesc(get(PPC::BC)); in PredicateInstruction()
2231 MI.setDesc(get(PPC::BCn)); in PredicateInstruction()
2239 MI.setDesc(get(PPC::BCC)); in PredicateInstruction()
2734 MI->setDesc(NewDesc); in optimizeCompareInstr()
2995 MI.setDesc(get(Opcode)); in expandVSXMemPseudo()
3081 MI.setDesc(get(PPC::LD)); in expandPostRAPseudo()
3092 MI.setDesc(get(PPC::STD)); in expandPostRAPseudo()
3101 MI.setDesc(get(PPC::LDX)); in expandPostRAPseudo()
3124 MI.setDesc(get(PPC::ISYNC)); in expandPostRAPseudo()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp378 MIB->setDesc(get(Move)); in ExpandMOVX_RR()
454 MIB->setDesc(Desc); in ExpandMOVSZX_RM()
493 MIB->setDesc(get(M68k::MOV16cd)); in ExpandCCR()
496 MIB->setDesc(get(M68k::MOV16dc)); in ExpandCCR()
564 MIB->setDesc(Desc); in Expand2AddrUndef()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp997 I.setDesc(TII.get(AArch64::COPY)); in selectCopy()
2503 I.setDesc(TII.get(Opc)); in select()
2617 I.setDesc(TII.get(MovOpc)); in select()
2882 I.setDesc(TII.get(NewOpc)); in select()
2965 I.setDesc(TII.get(NewOpc)); in select()
3015 I.setDesc(TII.get(NewOpc)); in select()
3319 I.setDesc(TII.get(NewOpc)); in select()
3514 I.setDesc(TII.get(Opc)); in selectReduction()
3528 I.setDesc(TII.get(Opc)); in selectReduction()
3715 I.setDesc(TII.get(Opc)); in selectIntrinsicTrunc()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCSymbolMachO.h105 void setDesc(unsigned Value) const { in setDesc() function
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.cpp122 MI->setDesc(TII->get(CSKY::SUBI32)); in IsLegalOffset()
281 MI->setDesc(TII->get(TargetOpcode::COPY)); in eliminateFrameIndex()

12345