Home
last modified time | relevance | path

Searched refs:rot (Results 1 – 25 of 32) sorted by relevance

12

/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dlegalize-rotr-rotl.mir16 ; CHECK: $w0 = COPY %rot(s32)
20 %rot:_(s32) = G_ROTR %0(s32), %1(s32)
21 $w0 = COPY %rot(s32)
37 ; CHECK: $x0 = COPY %rot(s64)
42 $x0 = COPY %rot(s64)
61 ; CHECK: $w0 = COPY %rot(s32)
66 $w0 = COPY %rot(s32)
84 ; CHECK: $x0 = COPY %rot(s64)
89 $x0 = COPY %rot(s64)
120 $q0 = COPY %rot(<4 x s32>)
[all …]
H A Dprelegalizercombiner-trivial-arith.mir358 %rot:_(s32) = G_ROTL %copy(s32), %zero(s32)
359 $w0 = COPY %rot(s32)
377 %rot:_(s32) = G_ROTR %copy(s32), %zero(s32)
378 $w0 = COPY %rot(s32)
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dicmp-fsh.ll15 %r = icmp eq i8 %rot, 0
29 call void @use(i8 %rot)
30 %r = icmp ne i8 %rot, 0
40 %r = icmp eq i8 %rot, -1
110 call void @use(i8 %rot)
111 %r = icmp eq i8 %rot, 0
121 %r = icmp ne i8 %rot, 0
131 %r = icmp eq i8 %rot, -1
141 %r = icmp ne i8 %rot, -1
154 %r = icmp ne i8 %rot, 1
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dsetcc-fsh.ll19 %r = icmp eq i8 %rot, 0
39 call void @use32(i32 %rot)
40 %r = icmp ne i32 %rot, 0
51 %r = icmp eq i8 %rot, -1
98 %r = icmp eq i16 %rot, 0
109 %r = icmp ne i64 %rot, 0
147 %r = icmp ne i64 %rot, 1
195 %or = or i8 %rot, %y
207 %or = or i64 %y, %rot
225 %or = or i32 %y, %rot
[all …]
H A Dwiden_load-2.ll350 define void @rot(ptr nocapture sret(%i8vec3pack) %result, ptr %X, ptr %rot) nounwind {
351 ; X86-LABEL: rot:
367 ; X64-LABEL: rot:
382 store <3 x i8> <i8 1, i8 1, i8 1>, ptr %rot
385 %tmp2 = load %i8vec3pack, ptr %rot
H A Dcombine-rotates.ll7 ; fold (rot (rot x, c1), c2) -> rot x, c1+c2
95 ; TODO - fold (select (icmp eq c, 0), x, (rot x, c)) -> rot x, c
H A Dfunnel-shift.ll1095 %rot = call i32 @llvm.fshl.i32(i32 %y, i32 %y, i32 %s)
1096 %or = or i32 %rot, %shx
1150 %rot = call i32 @llvm.fshl.i32(i32 %y, i32 %y, i32 %s)
1151 %or = or i32 %shx, %rot
1205 %rot = call i32 @llvm.fshr.i32(i32 %y, i32 %y, i32 %s)
1206 %or = or i32 %rot, %shx
1260 %rot = call i32 @llvm.fshr.i32(i32 %y, i32 %y, i32 %s)
1261 %or = or i32 %shx, %rot
/llvm-project-15.0.7/llvm/test/Transforms/LoopRotate/
H A Dnoalias.ll171 ; CHECK: !3 = distinct !{!3, !4, !"test_loop_rotate_XX: pA:pre.rot"}
176 ; CHECK: !8 = distinct !{!8, !4, !"test_loop_rotate_XX: pA:h.rot"}
178 ; CHECK: !10 = distinct !{!10, !4, !"test_loop_rotate_XX: pA:pre.rot"}
180 ; CHECK: !12 = distinct !{!12, !4, !"test_loop_rotate_XX: pA:h.rot"}
182 ; CHECK: !14 = distinct !{!14, !4, !"test_loop_rotate_XX: pA:pre.rot"}
184 ; CHECK: !16 = distinct !{!16, !4, !"test_loop_rotate_XX: pA:h.rot"}
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dfunnel-shift.ll375 %rot = call i32 @llvm.fshl.i32(i32 %y, i32 %y, i32 %s)
376 %or = or i32 %rot, %shx
407 %rot = call i32 @llvm.fshl.i32(i32 %y, i32 %y, i32 %s)
408 %or = or i32 %shx, %rot
438 %rot = call i32 @llvm.fshr.i32(i32 %y, i32 %y, i32 %s)
439 %or = or i32 %rot, %shx
469 %rot = call i32 @llvm.fshr.i32(i32 %y, i32 %y, i32 %s)
470 %or = or i32 %shx, %rot
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/
H A D2011-03-08-UnreachableUse.ll5 ; the transformations done by SimplifyCFG, so this test is likely to rot
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrThumb2.td1334 bits<2> rot;
1341 let Inst{5-4} = rot; // rotate
1369 bits<2> rot;
1375 let Inst{5-4} = rot;
2252 (t2SXTB rGPR:$Rn, rot_imm:$rot)>;
5205 def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
5207 def : InstAlias<"uxtb16${p} $Rd, $Rm$rot",
5210 def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
5213 def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
5215 def : InstAlias<"sxtb16${p} $Rd, $Rm$rot",
[all …]
H A DARMInstrInfo.td1809 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1814 bits<2> rot;
1817 let Inst{11-10} = rot;
1823 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1825 bits<2> rot;
1827 let Inst{11-10} = rot;
1841 bits<2> rot;
1844 let Inst{11-10} = rot;
1854 bits<2> rot;
1856 let Inst{11-10} = rot;
[all …]
H A DARMInstrMVE.td3660 bits<2> rot;
3664 let Inst{24-23} = rot;
3684 imm:$rot))>;
3795 bit rot;
3799 let Inst{24} = rot;
3818 imm:$rot))>;
4601 bits<2> rot;
4607 let Inst{12} = rot{1};
4610 let Inst{0} = rot{0};
5053 bit rot;
[all …]
H A DARMInstrNEON.td4925 bits<2> rot;
4926 let Inst{24-23} = rot;
4934 bits<1> rot;
4935 let Inst{24} = rot;
4943 bits<2> rot;
4946 let Inst{21-20} = rot;
4955 bits<2> rot;
4958 let Inst{21-20} = rot;
4991 (ins DPR:$Vn, DPR:$Vm, complexrotateopodd:$rot),
5029 complexrotateop:$rot),
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dinsert-06.ll74 %rot = or i32 %parta, %partb
75 %low = zext i32 %rot to i64
/llvm-project-15.0.7/lld/ELF/Arch/
H A DARM.cpp454 uint32_t rot = 0; in encodeAluGroup() local
457 rot = (lz + 8) << 7; in encodeAluGroup()
462 write32le(loc, (read32le(loc) & 0xff3ff000) | opcode | rot | (imm & 0xff)); in encodeAluGroup()
/llvm-project-15.0.7/lldb/examples/summaries/cocoa/
H A Dobjc_runtime.py196 self.rot = self.valobj.CreateValueFromData(
201 self.data = RoT_Data(self.rot, self.sys_params)
376 return self.rwt.rot.instance_size(align)
/llvm-project-15.0.7/llvm/lib/Support/
H A DAPInt.cpp1089 APInt rot = rotateAmt; in rotateModulo() local
1093 rot = rotateAmt.zext(BitWidth); in rotateModulo()
1095 rot = rot.urem(APInt(rot.getBitWidth(), BitWidth)); in rotateModulo()
1096 return rot.getLimitedValue(BitWidth); in rotateModulo()
/llvm-project-15.0.7/llvm/docs/
H A DSupportPolicy.rst66 * Bit-rot of a component in the core tier will result in that component being
87 bit-rot, and will be removed if the sub-community that cares about it
/llvm-project-15.0.7/llvm/test/Transforms/CodeGenPrepare/X86/
H A Dx86-shuffle-sink-inseltpoison.ll202 define void @funnel_splatvar(i32* nocapture %arr, i32 %rot) {
258 %broadcast.splatinsert15 = insertelement <8 x i32> poison, i32 %rot, i32 0
H A Dx86-shuffle-sink.ll202 define void @funnel_splatvar(i32* nocapture %arr, i32 %rot) {
258 %broadcast.splatinsert15 = insertelement <8 x i32> undef, i32 %rot, i32 0
H A Dvec-shift-inseltpoison.ll420 …%rot = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> %wide.load21, <8 x i32> %wide.load21, <8 x i32> %…
421 store <8 x i32> %rot, <8 x i32>* %t5, align 4
H A Dvec-shift.ll420 …%rot = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> %wide.load21, <8 x i32> %wide.load21, <8 x i32> %…
421 store <8 x i32> %rot, <8 x i32>* %t5, align 4
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Drv32zbp.ll974 %rot = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 16)
975 %or = or i32 %rot, %a
993 %or = or i32 %rot, %a
3223 %rot = call i32 @llvm.fshl.i32(i32 %y, i32 %y, i32 %s)
3224 %or = or i32 %rot, %shx
3263 %rot = call i32 @llvm.fshl.i32(i32 %y, i32 %y, i32 %s)
3264 %or = or i32 %shx, %rot
3303 %rot = call i32 @llvm.fshr.i32(i32 %y, i32 %y, i32 %s)
3304 %or = or i32 %rot, %shx
3343 %rot = call i32 @llvm.fshr.i32(i32 %y, i32 %y, i32 %s)
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td10746 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # ", $rot"
10747 "|" # kind # "\t$Rd, $Rn, $Rm, $rot}", "", pattern>,
10752 bits<1> rot;
10762 let Inst{12} = rot;
10820 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # ", $rot"
10826 bits<2> rot;
10835 let Inst{12-11} = rot;
10896 "$idx, $rot" # "|" # apple_kind #
10897 "\t$Rd, $Rn, $Rm$idx, $rot}", "$Rd = $dst", pattern>,
10902 bits<2> rot;
[all …]

12