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/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dselect-select.mir82 %reg1:gpr(s32) = COPY $w1
110 %reg1:gpr(s32) = COPY $w1
138 %reg1:gpr(s32) = COPY $w1
167 %reg1:gpr(s32) = COPY $w1
196 %reg1:gpr(s32) = COPY $w1
225 %reg1:gpr(s32) = COPY $w1
254 %reg1:gpr(s32) = COPY $w1
366 %reg1:gpr(s32) = COPY $w1
396 %reg1:gpr(s32) = COPY $w1
428 %reg1:gpr(s64) = COPY $x1
[all …]
H A Dspeculative-hardening-brcond.mir71 ; CHECK: %reg1:fpr32 = COPY $s1
72 ; CHECK: FCMPSrr %reg0, %reg1, implicit-def $nzcv
81 %reg1:fpr(s32) = COPY $s1
82 %cmp:gpr(s32) = G_FCMP floatpred(oeq), %reg0, %reg1
H A Dselect-cmp.mir207 ; CHECK-NEXT: %reg1:gpr64sp = COPY $x1
208 ; CHECK-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %reg1, %reg0, 18, implicit-def $nzcv
213 %reg1:gpr(s64) = COPY $x1
217 %cmp:gpr(s32) = G_ICMP intpred(ugt), %reg1(s64), %shift
236 ; CHECK-NEXT: %reg1:gpr32sp = COPY $w1
243 %reg1:gpr(s32) = COPY $w1
247 %cmp:gpr(s32) = G_ICMP intpred(ugt), %reg1(s32), %shift
267 ; CHECK-NEXT: %reg1:gpr64 = COPY $x1
270 ; CHECK-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs %reg1, %ext, 5, implicit-def $nzcv
275 %reg1:gpr(s64) = COPY $x1
[all …]
H A Dselect-uaddo.mir156 ; CHECK-NEXT: %reg1:gpr32 = COPY $w0
157 ; CHECK-NEXT: %add:gpr64 = ADDSXrx %reg0, %reg1, 18, implicit-def $nzcv
162 %reg1:gpr(s32) = COPY $w0
163 %ext:gpr(s64) = G_ZEXT %reg1(s32)
H A Dselect-saddo.mir156 ; CHECK-NEXT: %reg1:gpr32 = COPY $w0
157 ; CHECK-NEXT: %add:gpr64 = ADDSXrx %reg0, %reg1, 18, implicit-def $nzcv
162 %reg1:gpr(s32) = COPY $w0
163 %ext:gpr(s64) = G_ZEXT %reg1(s32)
H A Dselect-ssubo.mir156 ; CHECK-NEXT: %reg1:gpr32 = COPY $w0
157 ; CHECK-NEXT: %add:gpr64 = SUBSXrx %reg0, %reg1, 18, implicit-def $nzcv
162 %reg1:gpr(s32) = COPY $w0
163 %ext:gpr(s64) = G_ZEXT %reg1(s32)
H A Dselect-usubo.mir158 ; CHECK-NEXT: %reg1:gpr32 = COPY $w0
159 ; CHECK-NEXT: %add:gpr64 = SUBSXrx %reg0, %reg1, 18, implicit-def $nzcv
165 %reg1:gpr(s32) = COPY $w0
166 %ext:gpr(s64) = G_ZEXT %reg1(s32)
H A Dpostlegalizer-lowering-swap-compare-operands.mir78 %reg1:_(s64) = COPY $x1
604 ; LOWER: %reg1:_(s64) = COPY $x1
617 ; SELECT: %reg1:gpr64 = COPY $x1
631 %reg1:_(s64) = COPY $x1
632 %sext_in_reg:_(s64) = G_SEXT_INREG %reg1, 1
656 ; LOWER: %reg1:_(s64) = COPY $x1
658 ; LOWER: %and:_(s64) = G_AND %reg1, %and_mask
668 ; SELECT: %reg1:gpr64 = COPY $x1
669 ; SELECT: %and:gpr64common = ANDXri %reg1, 4103
678 %reg1:_(s64) = COPY $x1
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dmax-literals.ll6 define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %re…
8 %0 = extractelement <4 x float> %reg1, i32 0
9 %1 = extractelement <4 x float> %reg1, i32 1
10 %2 = extractelement <4 x float> %reg1, i32 2
11 %3 = extractelement <4 x float> %reg1, i32 3
35 define amdgpu_vs void @main2(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %r…
37 %0 = extractelement <4 x float> %reg1, i32 0
38 %1 = extractelement <4 x float> %reg1, i32 1
39 %2 = extractelement <4 x float> %reg1, i32 2
40 %3 = extractelement <4 x float> %reg1, i32 3
H A Dswizzle-export.ll9 define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) {
11 %0 = extractelement <4 x float> %reg1, i32 0
12 %1 = extractelement <4 x float> %reg1, i32 1
13 %2 = extractelement <4 x float> %reg1, i32 2
14 %3 = extractelement <4 x float> %reg1, i32 3
99 define amdgpu_vs void @main2(<4 x float> inreg %reg0, <4 x float> inreg %reg1) {
101 %0 = extractelement <4 x float> %reg1, i32 0
102 %1 = extractelement <4 x float> %reg1, i32 1
H A Dschedule-fs-loop.ll4 define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
6 %tmp = extractelement <4 x float> %reg1, i32 0
7 %tmp5 = extractelement <4 x float> %reg1, i32 1
8 %tmp6 = extractelement <4 x float> %reg1, i32 2
9 %tmp7 = extractelement <4 x float> %reg1, i32 3
H A Dschedule-fs-loop-nested-if.ll4 define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
6 %tmp = extractelement <4 x float> %reg1, i32 0
7 %tmp5 = extractelement <4 x float> %reg1, i32 1
8 %tmp6 = extractelement <4 x float> %reg1, i32 2
9 %tmp7 = extractelement <4 x float> %reg1, i32 3
H A Dpv-packing.ll4 define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %re…
25 %0 = extractelement <4 x float> %reg1, i32 0
26 %1 = extractelement <4 x float> %reg1, i32 1
27 %2 = extractelement <4 x float> %reg1, i32 2
H A Dr600cfg.ll3 define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) {
5 %0 = extractelement <4 x float> %reg1, i32 0
6 %1 = extractelement <4 x float> %reg1, i32 1
7 %2 = extractelement <4 x float> %reg1, i32 2
8 %3 = extractelement <4 x float> %reg1, i32 3
H A Drv7x0_count3.ll4 define amdgpu_vs void @test(<4 x float> inreg %reg0, <4 x float> inreg %reg1) {
6 %tmp = extractelement <4 x float> %reg1, i32 0
7 %tmp1 = extractelement <4 x float> %reg1, i32 1
8 %tmp2 = extractelement <4 x float> %reg1, i32 2
9 %tmp3 = extractelement <4 x float> %reg1, i32 3
H A Dload-input-fold.ll3 define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %re…
5 %0 = extractelement <4 x float> %reg1, i32 0
6 %1 = extractelement <4 x float> %reg1, i32 1
7 %2 = extractelement <4 x float> %reg1, i32 2
8 %3 = extractelement <4 x float> %reg1, i32 3
H A Dschedule-vs-if-nested-loop.ll4 define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) {
6 %0 = extractelement <4 x float> %reg1, i32 0
7 %1 = extractelement <4 x float> %reg1, i32 1
8 %2 = extractelement <4 x float> %reg1, i32 2
9 %3 = extractelement <4 x float> %reg1, i32 3
H A Dschedule-vs-if-nested-loop-failure.ll7 define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) {
9 %0 = extractelement <4 x float> %reg1, i32 0
10 %1 = extractelement <4 x float> %reg1, i32 2
37 %15 = extractelement <4 x float> %reg1, i32 1
38 %16 = extractelement <4 x float> %reg1, i32 3
H A Dllvm.pow.ll30 define amdgpu_ps void @test2(<4 x float> inreg %reg0, <4 x float> inreg %reg1) {
31 %vec = call <4 x float> @llvm.pow.v4f32( <4 x float> %reg0, <4 x float> %reg1)
/llvm-project-15.0.7/clang/test/CodeGen/
H A Daarch64-inline-asm.c60 register unsigned long reg1 asm("r1") = 1; in test_gcc_registers()
67 asm volatile("hvc #0" : : "r" (reg0), "r" (reg1)); in test_gcc_registers()
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/micromips-sizereduction/
H A Dmicromips-xor16.ll8 %reg1 = or i32 %a, %b
9 %reg2 = xor i32 %reg1, -1
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dirtranslator-readnone-intrinsic-callsite.ll13 %reg1 = call i32 @llvm.amdgcn.s.getreg(i32 0) #1
14 store volatile i32 %reg1, i32 addrspace(1)* undef
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dfast-isel-pic.ll19 ; ARM: ldr [[reg1:r[0-9]+]],
20 ; ARM: add [[reg1]], pc, [[reg1]]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Davoid_complex_am.ll4 ; On X86, reg1 + 1*reg2 has the same cost as reg1 + 8*reg2.
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dtls_get_addr_fence1.mir60 ; CHECK: %[[reg1:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDIStlsgdHA $x2, @tls_var
62 ; CHECK: $x3 = ADDItlsgdL %[[reg1]], @tls_var

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