1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=aarch64-apple-darwin -run-pass=instruction-select -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s
3
4...
5---
6name:            select_f32
7alignment:       4
8legalized:       true
9regBankSelected: true
10tracksRegLiveness: true
11machineFunctionInfo: {}
12body:             |
13  bb.0:
14    liveins: $s0, $s1, $w0
15
16    ; CHECK-LABEL: name: select_f32
17    ; CHECK: liveins: $s0, $s1, $w0
18    ; CHECK-NEXT: {{  $}}
19    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
20    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
21    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s1
22    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 0, implicit-def $nzcv
23    ; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[COPY2]], 1, implicit $nzcv
24    ; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
25    ; CHECK-NEXT: RET_ReallyLR implicit $s0
26    %0:gpr(s32) = COPY $w0
27    %1:fpr(s32) = COPY $s0
28    %2:fpr(s32) = COPY $s1
29    %4:fpr(s32) = G_SELECT %0, %1, %2
30    $s0 = COPY %4(s32)
31    RET_ReallyLR implicit $s0
32
33...
34---
35name:            select_f64
36alignment:       4
37legalized:       true
38regBankSelected: true
39tracksRegLiveness: true
40machineFunctionInfo: {}
41body:             |
42  bb.0:
43    liveins: $d0, $d1, $w0
44
45    ; CHECK-LABEL: name: select_f64
46    ; CHECK: liveins: $d0, $d1, $w0
47    ; CHECK-NEXT: {{  $}}
48    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
49    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
50    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d1
51    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 0, implicit-def $nzcv
52    ; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[COPY2]], 1, implicit $nzcv
53    ; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]
54    ; CHECK-NEXT: RET_ReallyLR implicit $d0
55    %0:gpr(s32) = COPY $w0
56    %1:fpr(s64) = COPY $d0
57    %2:fpr(s64) = COPY $d1
58    %4:fpr(s64) = G_SELECT %0, %1, %2
59    $d0 = COPY %4(s64)
60    RET_ReallyLR implicit $d0
61...
62---
63name:            csel
64legalized:       true
65regBankSelected: true
66tracksRegLiveness: true
67body:             |
68  bb.0:
69    liveins: $w0, $w1, $w2, $w3
70    ; CHECK-LABEL: name: csel
71    ; CHECK: liveins: $w0, $w1, $w2, $w3
72    ; CHECK-NEXT: {{  $}}
73    ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
74    ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
75    ; CHECK-NEXT: %t:gpr32 = COPY $w2
76    ; CHECK-NEXT: %f:gpr32 = COPY $w3
77    ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
78    ; CHECK-NEXT: %select:gpr32 = CSELWr %t, %f, 1, implicit $nzcv
79    ; CHECK-NEXT: $w0 = COPY %select
80    ; CHECK-NEXT: RET_ReallyLR implicit $w0
81    %reg0:gpr(s32) = COPY $w0
82    %reg1:gpr(s32) = COPY $w1
83    %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
84    %t:gpr(s32) = COPY $w2
85    %f:gpr(s32) = COPY $w3
86    %select:gpr(s32) = G_SELECT %cmp, %t, %f
87    $w0 = COPY %select(s32)
88    RET_ReallyLR implicit $w0
89...
90---
91name:            csinc_t_0_f_1
92legalized:       true
93regBankSelected: true
94tracksRegLiveness: true
95body:             |
96  bb.0:
97    liveins: $w0, $w1
98    ; G_SELECT cc, 0, 1 -> CSINC zreg, zreg, cc
99
100    ; CHECK-LABEL: name: csinc_t_0_f_1
101    ; CHECK: liveins: $w0, $w1
102    ; CHECK-NEXT: {{  $}}
103    ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
104    ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
105    ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
106    ; CHECK-NEXT: %select:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
107    ; CHECK-NEXT: $w0 = COPY %select
108    ; CHECK-NEXT: RET_ReallyLR implicit $w0
109    %reg0:gpr(s32) = COPY $w0
110    %reg1:gpr(s32) = COPY $w1
111    %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
112    %t:gpr(s32) = G_CONSTANT i32 0
113    %f:gpr(s32) = G_CONSTANT i32 1
114    %select:gpr(s32) = G_SELECT %cmp, %t, %f
115    $w0 = COPY %select(s32)
116    RET_ReallyLR implicit $w0
117...
118---
119name:            csinv_t_0_f_neg_1
120legalized:       true
121regBankSelected: true
122tracksRegLiveness: true
123body:             |
124  bb.0:
125    liveins: $w0, $w1
126    ; G_SELECT cc 0, -1 -> CSINV zreg, zreg cc
127
128    ; CHECK-LABEL: name: csinv_t_0_f_neg_1
129    ; CHECK: liveins: $w0, $w1
130    ; CHECK-NEXT: {{  $}}
131    ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
132    ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
133    ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
134    ; CHECK-NEXT: %select:gpr32 = CSINVWr $wzr, $wzr, 1, implicit $nzcv
135    ; CHECK-NEXT: $w0 = COPY %select
136    ; CHECK-NEXT: RET_ReallyLR implicit $w0
137    %reg0:gpr(s32) = COPY $w0
138    %reg1:gpr(s32) = COPY $w1
139    %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
140    %t:gpr(s32) = G_CONSTANT i32 0
141    %f:gpr(s32) = G_CONSTANT i32 -1
142    %select:gpr(s32) = G_SELECT %cmp, %t, %f
143    $w0 = COPY %select(s32)
144    RET_ReallyLR implicit $w0
145...
146---
147name:            csinc_t_1
148legalized:       true
149regBankSelected: true
150tracksRegLiveness: true
151body:             |
152  bb.0:
153    liveins: $w0, $w1, $w2
154    ; G_SELECT cc, 1, f -> CSINC f, zreg, inv_cc
155
156    ; CHECK-LABEL: name: csinc_t_1
157    ; CHECK: liveins: $w0, $w1, $w2
158    ; CHECK-NEXT: {{  $}}
159    ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
160    ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
161    ; CHECK-NEXT: %f:gpr32 = COPY $w2
162    ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
163    ; CHECK-NEXT: %select:gpr32 = CSINCWr %f, $wzr, 0, implicit $nzcv
164    ; CHECK-NEXT: $w0 = COPY %select
165    ; CHECK-NEXT: RET_ReallyLR implicit $w0
166    %reg0:gpr(s32) = COPY $w0
167    %reg1:gpr(s32) = COPY $w1
168    %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
169    %t:gpr(s32) = G_CONSTANT i32 1
170    %f:gpr(s32) = COPY $w2
171    %select:gpr(s32) = G_SELECT %cmp, %t, %f
172    $w0 = COPY %select(s32)
173    RET_ReallyLR implicit $w0
174...
175---
176name:            csinv_t_neg_1
177legalized:       true
178regBankSelected: true
179tracksRegLiveness: true
180body:             |
181  bb.0:
182    liveins: $w0, $w1, $w2
183    ; G_SELECT cc, -1, f -> CSINV f, zreg, inv_cc
184
185    ; CHECK-LABEL: name: csinv_t_neg_1
186    ; CHECK: liveins: $w0, $w1, $w2
187    ; CHECK-NEXT: {{  $}}
188    ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
189    ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
190    ; CHECK-NEXT: %f:gpr32 = COPY $w2
191    ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
192    ; CHECK-NEXT: %select:gpr32 = CSINVWr %f, $wzr, 0, implicit $nzcv
193    ; CHECK-NEXT: $w0 = COPY %select
194    ; CHECK-NEXT: RET_ReallyLR implicit $w0
195    %reg0:gpr(s32) = COPY $w0
196    %reg1:gpr(s32) = COPY $w1
197    %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
198    %t:gpr(s32) = G_CONSTANT i32 -1
199    %f:gpr(s32) = COPY $w2
200    %select:gpr(s32) = G_SELECT %cmp, %t, %f
201    $w0 = COPY %select(s32)
202    RET_ReallyLR implicit $w0
203...
204---
205name:            csinc_f_1
206legalized:       true
207regBankSelected: true
208tracksRegLiveness: true
209body:             |
210  bb.0:
211    liveins: $w0, $w1, $w2
212    ; G_SELECT cc, t, 1 -> CSINC t, zreg, cc
213
214    ; CHECK-LABEL: name: csinc_f_1
215    ; CHECK: liveins: $w0, $w1, $w2
216    ; CHECK-NEXT: {{  $}}
217    ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
218    ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
219    ; CHECK-NEXT: %t:gpr32 = COPY $w2
220    ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
221    ; CHECK-NEXT: %select:gpr32 = CSINCWr %t, $wzr, 1, implicit $nzcv
222    ; CHECK-NEXT: $w0 = COPY %select
223    ; CHECK-NEXT: RET_ReallyLR implicit $w0
224    %reg0:gpr(s32) = COPY $w0
225    %reg1:gpr(s32) = COPY $w1
226    %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
227    %t:gpr(s32) = COPY $w2
228    %f:gpr(s32) = G_CONSTANT i32 1
229    %select:gpr(s32) = G_SELECT %cmp, %t, %f
230    $w0 = COPY %select(s32)
231    RET_ReallyLR implicit $w0
232...
233---
234name:            csinc_f_neg_1
235legalized:       true
236regBankSelected: true
237tracksRegLiveness: true
238body:             |
239  bb.0:
240    liveins: $w0, $w1, $w2
241    ; G_SELECT cc, t, -1 -> CSINC t, zreg, cc
242
243    ; CHECK-LABEL: name: csinc_f_neg_1
244    ; CHECK: liveins: $w0, $w1, $w2
245    ; CHECK-NEXT: {{  $}}
246    ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
247    ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
248    ; CHECK-NEXT: %t:gpr32 = COPY $w2
249    ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
250    ; CHECK-NEXT: %select:gpr32 = CSINVWr %t, $wzr, 1, implicit $nzcv
251    ; CHECK-NEXT: $w0 = COPY %select
252    ; CHECK-NEXT: RET_ReallyLR implicit $w0
253    %reg0:gpr(s32) = COPY $w0
254    %reg1:gpr(s32) = COPY $w1
255    %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
256    %t:gpr(s32) = COPY $w2
257    %f:gpr(s32) = G_CONSTANT i32 -1
258    %select:gpr(s32) = G_SELECT %cmp, %t, %f
259    $w0 = COPY %select(s32)
260    RET_ReallyLR implicit $w0
261...
262---
263name:            csinc_t_1_no_cmp
264legalized:       true
265regBankSelected: true
266tracksRegLiveness: true
267body:             |
268  bb.0:
269    liveins: $w0, $w1
270    ; G_SELECT cc, 1, f -> CSINC f, zreg, inv_cc
271
272    ; CHECK-LABEL: name: csinc_t_1_no_cmp
273    ; CHECK: liveins: $w0, $w1
274    ; CHECK-NEXT: {{  $}}
275    ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
276    ; CHECK-NEXT: %f:gpr32 = COPY $w1
277    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
278    ; CHECK-NEXT: %select:gpr32 = CSINCWr %f, $wzr, 0, implicit $nzcv
279    ; CHECK-NEXT: $w0 = COPY %select
280    ; CHECK-NEXT: RET_ReallyLR implicit $w0
281    %reg0:gpr(s32) = COPY $w0
282    %t:gpr(s32) = G_CONSTANT i32 1
283    %f:gpr(s32) = COPY $w1
284    %select:gpr(s32) = G_SELECT %reg0, %t, %f
285    $w0 = COPY %select(s32)
286    RET_ReallyLR implicit $w0
287
288...
289---
290name:            csinc_f_1_no_cmp
291legalized:       true
292regBankSelected: true
293tracksRegLiveness: true
294body:             |
295  bb.0:
296    liveins: $w0, $w1
297    ; G_SELECT cc, t, 1 -> CSINC t, zreg, cc
298
299    ; CHECK-LABEL: name: csinc_f_1_no_cmp
300    ; CHECK: liveins: $w0, $w1
301    ; CHECK-NEXT: {{  $}}
302    ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
303    ; CHECK-NEXT: %t:gpr32 = COPY $w1
304    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
305    ; CHECK-NEXT: %select:gpr32 = CSINCWr %t, $wzr, 1, implicit $nzcv
306    ; CHECK-NEXT: $w0 = COPY %select
307    ; CHECK-NEXT: RET_ReallyLR implicit $w0
308    %reg0:gpr(s32) = COPY $w0
309    %t:gpr(s32) = COPY $w1
310    %f:gpr(s32) = G_CONSTANT i32 1
311    %select:gpr(s32) = G_SELECT %reg0, %t, %f
312    $w0 = COPY %select(s32)
313    RET_ReallyLR implicit $w0
314
315...
316---
317name:            csinc_t_1_no_cmp_s64
318legalized:       true
319regBankSelected: true
320tracksRegLiveness: true
321body:             |
322  bb.0:
323    liveins: $x0, $x1
324    ; G_SELECT cc, 1, f -> CSINC f, zreg, inv_cc
325
326    ; CHECK-LABEL: name: csinc_t_1_no_cmp_s64
327    ; CHECK: liveins: $x0, $x1
328    ; CHECK-NEXT: {{  $}}
329    ; CHECK-NEXT: %reg0:gpr64sp = COPY $x0
330    ; CHECK-NEXT: %cond:gpr32common = COPY %reg0.sub_32
331    ; CHECK-NEXT: %f:gpr64 = COPY $x1
332    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv
333    ; CHECK-NEXT: %select:gpr64 = CSINCXr %f, $xzr, 0, implicit $nzcv
334    ; CHECK-NEXT: $x0 = COPY %select
335    ; CHECK-NEXT: RET_ReallyLR implicit $x0
336    %reg0:gpr(s64) = COPY $x0
337    %cond:gpr(s32) = G_TRUNC %reg0(s64)
338    %t:gpr(s64) = G_CONSTANT i64 1
339    %f:gpr(s64) = COPY $x1
340    %select:gpr(s64) = G_SELECT %cond, %t, %f
341    $x0 = COPY %select(s64)
342    RET_ReallyLR implicit $x0
343
344...
345---
346name:            csneg_s32
347legalized:       true
348regBankSelected: true
349tracksRegLiveness: true
350body:             |
351  bb.0:
352    liveins: $w0, $w1, $w2
353    ; G_SELECT cc, true, (G_SUB 0, x) -> CSNEG true, x, cc
354
355    ; CHECK-LABEL: name: csneg_s32
356    ; CHECK: liveins: $w0, $w1, $w2
357    ; CHECK-NEXT: {{  $}}
358    ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
359    ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
360    ; CHECK-NEXT: %t:gpr32 = COPY $w2
361    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
362    ; CHECK-NEXT: %select:gpr32 = CSNEGWr %t, %reg1, 1, implicit $nzcv
363    ; CHECK-NEXT: $w0 = COPY %select
364    ; CHECK-NEXT: RET_ReallyLR implicit $w0
365    %reg0:gpr(s32) = COPY $w0
366    %reg1:gpr(s32) = COPY $w1
367    %t:gpr(s32) = COPY $w2
368    %zero:gpr(s32) = G_CONSTANT i32 0
369    %sub:gpr(s32) = G_SUB %zero(s32), %reg1
370    %select:gpr(s32) = G_SELECT %reg0, %t, %sub
371    $w0 = COPY %select(s32)
372    RET_ReallyLR implicit $w0
373
374...
375---
376name:            csneg_inverted_cc
377legalized:       true
378regBankSelected: true
379tracksRegLiveness: true
380body:             |
381  bb.0:
382    liveins: $w0, $w1, $w2
383    ; G_SELECT cc, (G_SUB 0, %x), %false -> CSNEG %x, %false, inv_cc
384
385    ; CHECK-LABEL: name: csneg_inverted_cc
386    ; CHECK: liveins: $w0, $w1, $w2
387    ; CHECK-NEXT: {{  $}}
388    ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
389    ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
390    ; CHECK-NEXT: %f:gpr32 = COPY $w2
391    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
392    ; CHECK-NEXT: %select:gpr32 = CSNEGWr %f, %reg1, 0, implicit $nzcv
393    ; CHECK-NEXT: $w0 = COPY %select
394    ; CHECK-NEXT: RET_ReallyLR implicit $w0
395    %reg0:gpr(s32) = COPY $w0
396    %reg1:gpr(s32) = COPY $w1
397    %f:gpr(s32) = COPY $w2
398    %zero:gpr(s32) = G_CONSTANT i32 0
399    %sub:gpr(s32) = G_SUB %zero(s32), %reg1
400    %select:gpr(s32) = G_SELECT %reg0, %sub, %f
401    $w0 = COPY %select(s32)
402    RET_ReallyLR implicit $w0
403
404...
405---
406name:            csneg_s64
407legalized:       true
408regBankSelected: true
409tracksRegLiveness: true
410body:             |
411  bb.0:
412    liveins: $x0, $x1, $x2
413    ; G_SELECT cc, true, (G_SUB 0, x) -> CSNEG true, x, cc
414
415    ; CHECK-LABEL: name: csneg_s64
416    ; CHECK: liveins: $x0, $x1, $x2
417    ; CHECK-NEXT: {{  $}}
418    ; CHECK-NEXT: %reg0:gpr64sp = COPY $x0
419    ; CHECK-NEXT: %cond:gpr32common = COPY %reg0.sub_32
420    ; CHECK-NEXT: %reg1:gpr64 = COPY $x1
421    ; CHECK-NEXT: %t:gpr64 = COPY $x2
422    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv
423    ; CHECK-NEXT: %select:gpr64 = CSNEGXr %t, %reg1, 1, implicit $nzcv
424    ; CHECK-NEXT: $x0 = COPY %select
425    ; CHECK-NEXT: RET_ReallyLR implicit $x0
426    %reg0:gpr(s64) = COPY $x0
427    %cond:gpr(s32) = G_TRUNC %reg0(s64)
428    %reg1:gpr(s64) = COPY $x1
429    %t:gpr(s64) = COPY $x2
430    %zero:gpr(s64) = G_CONSTANT i64 0
431    %sub:gpr(s64) = G_SUB %zero(s64), %reg1
432    %select:gpr(s64) = G_SELECT %cond, %t, %sub
433    $x0 = COPY %select(s64)
434    RET_ReallyLR implicit $x0
435...
436---
437name:            csneg_with_true_cst
438legalized:       true
439regBankSelected: true
440tracksRegLiveness: true
441body:             |
442  bb.0:
443    liveins: $w0, $w1, $w2
444    ; We should prefer eliminating the G_SUB over eliminating the constant true
445    ; value.
446
447    ; CHECK-LABEL: name: csneg_with_true_cst
448    ; CHECK: liveins: $w0, $w1, $w2
449    ; CHECK-NEXT: {{  $}}
450    ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
451    ; CHECK-NEXT: %t:gpr32 = MOVi32imm 1
452    ; CHECK-NEXT: %reg2:gpr32 = COPY $w2
453    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
454    ; CHECK-NEXT: %select:gpr32 = CSNEGWr %t, %reg2, 1, implicit $nzcv
455    ; CHECK-NEXT: $w0 = COPY %select
456    ; CHECK-NEXT: RET_ReallyLR implicit $w0
457    %reg0:gpr(s32) = COPY $w0
458    %reg1:gpr(s32) = COPY $w1
459    %t:gpr(s32) = G_CONSTANT i32 1
460    %zero:gpr(s32) = G_CONSTANT i32 0
461    %reg2:gpr(s32) = COPY $w2
462    %sub:gpr(s32) = G_SUB %zero(s32), %reg2
463    %select:gpr(s32) = G_SELECT %reg0, %t, %sub
464    $w0 = COPY %select(s32)
465    RET_ReallyLR implicit $w0
466...
467---
468name:            csinv_s32
469legalized:       true
470regBankSelected: true
471tracksRegLiveness: true
472body:             |
473  bb.0:
474    liveins: $w0, $w1, $w2
475    ; G_SELECT cc, true, (G_XOR x, -1) -> CSINV true, x, cc
476
477    ; CHECK-LABEL: name: csinv_s32
478    ; CHECK: liveins: $w0, $w1, $w2
479    ; CHECK-NEXT: {{  $}}
480    ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
481    ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
482    ; CHECK-NEXT: %t:gpr32 = COPY $w2
483    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
484    ; CHECK-NEXT: %select:gpr32 = CSINVWr %t, %reg1, 1, implicit $nzcv
485    ; CHECK-NEXT: $w0 = COPY %select
486    ; CHECK-NEXT: RET_ReallyLR implicit $w0
487    %reg0:gpr(s32) = COPY $w0
488    %reg1:gpr(s32) = COPY $w1
489    %t:gpr(s32) = COPY $w2
490    %negative_one:gpr(s32) = G_CONSTANT i32 -1
491    %xor:gpr(s32) = G_XOR %reg1(s32), %negative_one
492    %select:gpr(s32) = G_SELECT %reg0, %t, %xor
493    $w0 = COPY %select(s32)
494    RET_ReallyLR implicit $w0
495
496...
497---
498name:            csinv_inverted_cc
499legalized:       true
500regBankSelected: true
501tracksRegLiveness: true
502body:             |
503  bb.0:
504    liveins: $w0, $w1, $w2
505    ; G_SELECT cc, (G_XOR x, -1), %false -> CSINV %x, %false, inv_cc
506
507    ; CHECK-LABEL: name: csinv_inverted_cc
508    ; CHECK: liveins: $w0, $w1, $w2
509    ; CHECK-NEXT: {{  $}}
510    ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
511    ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
512    ; CHECK-NEXT: %f:gpr32 = COPY $w2
513    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
514    ; CHECK-NEXT: %select:gpr32 = CSINVWr %f, %reg1, 0, implicit $nzcv
515    ; CHECK-NEXT: $w0 = COPY %select
516    ; CHECK-NEXT: RET_ReallyLR implicit $w0
517    %reg0:gpr(s32) = COPY $w0
518    %reg1:gpr(s32) = COPY $w1
519    %f:gpr(s32) = COPY $w2
520    %negative_one:gpr(s32) = G_CONSTANT i32 -1
521    %xor:gpr(s32) = G_XOR %reg1(s32), %negative_one
522    %select:gpr(s32) = G_SELECT %reg0, %xor, %f
523    $w0 = COPY %select(s32)
524    RET_ReallyLR implicit $w0
525
526...
527---
528name:            csinv_s64
529legalized:       true
530regBankSelected: true
531tracksRegLiveness: true
532body:             |
533  bb.0:
534    liveins: $x0, $x1, $x2
535    ; G_SELECT cc, true, (G_XOR x, -1) -> CSINV true, x, cc
536
537    ; CHECK-LABEL: name: csinv_s64
538    ; CHECK: liveins: $x0, $x1, $x2
539    ; CHECK-NEXT: {{  $}}
540    ; CHECK-NEXT: %reg0:gpr64sp = COPY $x0
541    ; CHECK-NEXT: %reg1:gpr64 = COPY $x1
542    ; CHECK-NEXT: %cond:gpr32common = COPY %reg0.sub_32
543    ; CHECK-NEXT: %t:gpr64 = COPY $x2
544    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv
545    ; CHECK-NEXT: %select:gpr64 = CSINVXr %t, %reg1, 1, implicit $nzcv
546    ; CHECK-NEXT: $x0 = COPY %select
547    ; CHECK-NEXT: RET_ReallyLR implicit $x0
548    %reg0:gpr(s64) = COPY $x0
549    %reg1:gpr(s64) = COPY $x1
550    %cond:gpr(s32) = G_TRUNC %reg0(s64)
551    %t:gpr(s64) = COPY $x2
552    %negative_one:gpr(s64) = G_CONSTANT i64 -1
553    %xor:gpr(s64) = G_XOR %reg1(s64), %negative_one
554    %select:gpr(s64) = G_SELECT %cond, %t, %xor
555    $x0 = COPY %select(s64)
556    RET_ReallyLR implicit $x0
557
558...
559---
560name:            xor_not_negative_one
561legalized:       true
562regBankSelected: true
563tracksRegLiveness: true
564body:             |
565  bb.0:
566    liveins: $x0, $x1, $x2
567    ; zext(s32 -1) != s64 -1, so we can't fold it away.
568
569    ; CHECK-LABEL: name: xor_not_negative_one
570    ; CHECK: liveins: $x0, $x1, $x2
571    ; CHECK-NEXT: {{  $}}
572    ; CHECK-NEXT: %reg0:gpr64sp = COPY $x0
573    ; CHECK-NEXT: %reg1:gpr64 = COPY $x1
574    ; CHECK-NEXT: %cond:gpr32common = COPY %reg0.sub_32
575    ; CHECK-NEXT: %t:gpr64 = COPY $x2
576    ; CHECK-NEXT: %negative_one:gpr32 = MOVi32imm -1
577    ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG 0, %negative_one, %subreg.sub_32
578    ; CHECK-NEXT: %xor:gpr64 = EORXrr %reg1, %zext
579    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv
580    ; CHECK-NEXT: %select:gpr64 = CSELXr %t, %xor, 1, implicit $nzcv
581    ; CHECK-NEXT: $x0 = COPY %select
582    ; CHECK-NEXT: RET_ReallyLR implicit $x0
583    %reg0:gpr(s64) = COPY $x0
584    %reg1:gpr(s64) = COPY $x1
585    %cond:gpr(s32) = G_TRUNC %reg0(s64)
586    %t:gpr(s64) = COPY $x2
587    %negative_one:gpr(s32) = G_CONSTANT i32 -1
588    %zext:gpr(s64) = G_ZEXT %negative_one(s32)
589    %xor:gpr(s64) = G_XOR %reg1(s64), %zext
590    %select:gpr(s64) = G_SELECT %cond(s32), %t, %xor
591    $x0 = COPY %select(s64)
592    RET_ReallyLR implicit $x0
593
594...
595---
596name:            csinc_s32
597legalized:       true
598regBankSelected: true
599tracksRegLiveness: true
600body:             |
601  bb.0:
602    liveins: $w0, $w1, $w2
603    ; G_SELECT cc, %true, (G_ADD %x, 1) -> CSINC %true, %x, cc
604    ; CHECK-LABEL: name: csinc_s32
605    ; CHECK: liveins: $w0, $w1, $w2
606    ; CHECK-NEXT: {{  $}}
607    ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
608    ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
609    ; CHECK-NEXT: %t:gpr32 = COPY $w2
610    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
611    ; CHECK-NEXT: %select:gpr32 = CSINCWr %t, %reg1, 1, implicit $nzcv
612    ; CHECK-NEXT: $w0 = COPY %select
613    ; CHECK-NEXT: RET_ReallyLR implicit $w0
614    %reg0:gpr(s32) = COPY $w0
615    %reg1:gpr(s32) = COPY $w1
616    %t:gpr(s32) = COPY $w2
617    %one:gpr(s32) = G_CONSTANT i32 1
618    %add:gpr(s32) = G_ADD %reg1(s32), %one
619    %select:gpr(s32) = G_SELECT %reg0, %t, %add
620    $w0 = COPY %select(s32)
621    RET_ReallyLR implicit $w0
622
623...
624---
625name:            csinc_s32_inverted_cc
626legalized:       true
627regBankSelected: true
628tracksRegLiveness: true
629body:             |
630  bb.0:
631    liveins: $w0, $w1, $w2
632    ; G_SELECT cc, (G_ADD %x, 1), %false -> CSINC %x, %false, inv_cc
633    ; CHECK-LABEL: name: csinc_s32_inverted_cc
634    ; CHECK: liveins: $w0, $w1, $w2
635    ; CHECK-NEXT: {{  $}}
636    ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
637    ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
638    ; CHECK-NEXT: %f:gpr32 = COPY $w2
639    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
640    ; CHECK-NEXT: %select:gpr32 = CSINCWr %f, %reg1, 0, implicit $nzcv
641    ; CHECK-NEXT: $w0 = COPY %select
642    ; CHECK-NEXT: RET_ReallyLR implicit $w0
643    %reg0:gpr(s32) = COPY $w0
644    %reg1:gpr(s32) = COPY $w1
645    %f:gpr(s32) = COPY $w2
646    %one:gpr(s32) = G_CONSTANT i32 1
647    %add:gpr(s32) = G_ADD %reg1(s32), %one
648    %select:gpr(s32) = G_SELECT %reg0, %add, %f
649    $w0 = COPY %select(s32)
650    RET_ReallyLR implicit $w0
651
652...
653---
654name:            csinc_ptr_add
655legalized:       true
656regBankSelected: true
657tracksRegLiveness: true
658body:             |
659  bb.0:
660    liveins: $x0, $x1, $x2
661    ; G_SELECT cc, %true, (G_PTR_ADD %x, 1) -> CSINC %true, %x, cc
662
663    ; CHECK-LABEL: name: csinc_ptr_add
664    ; CHECK: liveins: $x0, $x1, $x2
665    ; CHECK-NEXT: {{  $}}
666    ; CHECK-NEXT: %reg0:gpr64sp = COPY $x0
667    ; CHECK-NEXT: %reg1:gpr64 = COPY $x1
668    ; CHECK-NEXT: %cond:gpr32common = COPY %reg0.sub_32
669    ; CHECK-NEXT: %t:gpr64 = COPY $x2
670    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv
671    ; CHECK-NEXT: %select:gpr64 = CSINCXr %t, %reg1, 1, implicit $nzcv
672    ; CHECK-NEXT: $x0 = COPY %select
673    ; CHECK-NEXT: RET_ReallyLR implicit $x0
674    %reg0:gpr(s64) = COPY $x0
675    %reg1:gpr(p0) = COPY $x1
676    %cond:gpr(s32) = G_TRUNC %reg0(s64)
677    %t:gpr(p0) = COPY $x2
678    %one:gpr(s64) = G_CONSTANT i64 1
679    %ptr_add:gpr(p0) = G_PTR_ADD %reg1(p0), %one
680    %select:gpr(p0) = G_SELECT %cond(s32), %t, %ptr_add
681    $x0 = COPY %select(p0)
682    RET_ReallyLR implicit $x0
683
684...
685---
686name:            binop_dont_optimize_twice
687legalized:       true
688regBankSelected: true
689tracksRegLiveness: true
690body:             |
691  bb.0:
692    liveins: $w0, $w1, $w2
693    ; CHECK-LABEL: name: binop_dont_optimize_twice
694    ; CHECK: liveins: $w0, $w1, $w2
695    ; CHECK-NEXT: {{  $}}
696    ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
697    ; CHECK-NEXT: %reg1:gpr32 = COPY $w1
698    ; CHECK-NEXT: %reg2:gpr32 = COPY $w2
699    ; CHECK-NEXT: %xor:gpr32 = ORNWrr $wzr, %reg1
700    ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
701    ; CHECK-NEXT: %select:gpr32 = CSNEGWr %xor, %reg2, 1, implicit $nzcv
702    ; CHECK-NEXT: $w0 = COPY %select
703    ; CHECK-NEXT: RET_ReallyLR implicit $w0
704    %reg0:gpr(s32) = COPY $w0
705    %reg1:gpr(s32) = COPY $w1
706    %reg2:gpr(s32) = COPY $w2
707    %f:gpr(s32) = COPY $w2
708    %negative_one:gpr(s32) = G_CONSTANT i32 -1
709    %xor:gpr(s32) = G_XOR %reg1(s32), %negative_one
710    %zero:gpr(s32) = G_CONSTANT i32 0
711    %sub:gpr(s32) = G_SUB %zero(s32), %reg2
712    %select:gpr(s32) = G_SELECT %reg0, %xor, %sub
713    $w0 = COPY %select(s32)
714    RET_ReallyLR implicit $w0
715