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Searched refs:liveAt (Results 1 – 18 of 18) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DGCNRegPressure.cpp37 if (!S.liveAt(SI)) continue; in printLivesAt()
46 } else if (LI.liveAt(SI)) { in printLivesAt()
252 if (S.liveAt(SI)) { in getLiveLaneMask()
257 } else if (LI.liveAt(SI)) { in getLiveLaneMask()
370 if (!S.liveAt(SI)) { in advanceBeforeNext()
376 } else if (!LI.liveAt(SI)) { in advanceBeforeNext()
H A DSIFormMemoryClauses.cpp357 if (!LI.liveAt(ClauseLiveOutIdx)) { in runOnMachineFunction()
364 if (SR.liveAt(ClauseLiveInIdx) && !SR.liveAt(ClauseLiveOutIdx)) in runOnMachineFunction()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DVirtRegMap.cpp394 assert(LI.liveAt(BaseIndex) && in readsUndefSubreg()
401 if ((SR.LaneMask & UseMask).any() && SR.liveAt(BaseIndex)) in readsUndefSubreg()
529 if (UnitRange.liveAt(AfterMIDefs) && UnitRange.liveAt(BeforeMIUses)) in subRegLiveThrough()
H A DRegisterCoalescer.cpp1471 if (!SR.liveAt(DefIndex)) in reMaterializeTrivialDef()
1632 if (SR.liveAt(Idx)) in eliminateUndefCopy()
1635 } else if (SrcLI.liveAt(Idx)) in eliminateUndefCopy()
1693 if (SR.liveAt(UseIdx)) { in eliminateUndefCopy()
1699 isLive = DstLI.liveAt(UseIdx); in eliminateUndefCopy()
1728 if (S.liveAt(UseIdx)) { in addUndefFlag()
1784 Reads = DstInt->liveAt(LIS->getInstructionIndex(*UseMI)); in updateRegDefsUses()
1881 if (!S.liveAt(Pos) && (PrunedLanes & SubRegMask).any()) { in setUndefOnPrunedSubRegUses()
H A DRenameIndependentSubregs.cpp293 if (SR.liveAt(Pos)) in subRangeLiveAt()
H A DLiveRangeEdit.cpp143 if (!SR.liveAt(UseIdx)) in allUsesAvailableAt()
H A DSplitKit.cpp613 if (S.liveAt(UseIdx)) in defFromParent()
1256 if (PSR.liveAt(LastUse)) in extendPHIRange()
1351 if (!Edit->getParent().liveAt(Idx.getPrevSlot())) in rewriteAssigned()
H A DPHIElimination.cpp753 if (LI.liveAt(LIS->getMBBStartIdx(SI))) in isLiveOutPastPHIs()
H A DMachineBasicBlock.cpp1193 if (!LI.liveAt(PrevIndex)) in SplitCriticalEdge()
1196 bool isLiveOut = LI.liveAt(LIS->getMBBStartIdx(Succ)); in SplitCriticalEdge()
H A DRegisterPressure.cpp457 return LR.liveAt(Pos); in getLiveLanesAt()
1251 return LR.liveAt(Pos); in getLiveLanesAt()
H A DMachineVerifier.cpp2206 if (loads && !LI.liveAt(Idx.getRegSlot(true))) { in visitMachineOperand()
2210 if (stores && !LI.liveAt(Idx.getRegSlot())) { in visitMachineOperand()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DLiveIntervals.h241 return LR.liveAt(getMBBStartIdx(mbb)); in isLiveInToMBB()
246 return LR.liveAt(getMBBEndIdx(mbb).getPrevSlot()); in isLiveOutOfMBB()
H A DLiveInterval.h401 bool liveAt(SlotIndex index) const { in liveAt() function
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMemIntrinsicResults.cpp139 if (!FromLI->liveAt(FromIdx.getDeadSlot())) in replaceDominatedUses()
H A DWebAssemblyRegStackify.cpp587 IsDead = !LI.liveAt(LIS.getInstructionIndex(Def).getDeadSlot()); in rematerializeCheapDef()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp213 !LIS->getInterval(AddendSrcReg).liveAt(FMAIdx)) in processBlock()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonExpandCondsets.cpp489 if (!Seg.start.isRegister() || !Range.liveAt(Seg.start.getPrevSlot())) in updateDeadsInRange()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp1022 CCLiveAtMI = CCLiveRange->liveAt(MISlot); in foldMemoryOperandImpl()