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Searched refs:isWave32 (Results 1 – 25 of 33) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h34 bool isWave32; variable
332 return isWave32 ? &AMDGPU::SReg_32RegClass in getBoolRC()
337 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass in getWaveMaskRegClass()
H A DSILateBranchLowering.cpp141 MovOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in runOnMachineFunction()
142 ExecReg = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in runOnMachineFunction()
H A DAMDGPUAtomicOptimizer.cpp311 if (ST->isWave32()) in buildReduction()
372 if (!ST->isWave32()) { in buildScan()
417 if (!ST->isWave32()) { in buildShiftRight()
510 if (ST->isWave32()) { in optimizeAtomic()
H A DSIOptimizeExecMasking.cpp624 ST->isWave32() ? AMDGPU::S_AND_SAVEEXEC_B32 : AMDGPU::S_AND_SAVEEXEC_B64; in tryRecordVCmpxAndSaveexecSequence()
710 ST->isWave32() ? AMDGPU::S_XOR_B32 : AMDGPU::S_XOR_B64; in tryRecordOrSaveexecXorSequence()
720 const unsigned OrSaveexecOpcode = ST->isWave32() in tryRecordOrSaveexecXorSequence()
748 const unsigned Andn2Opcode = ST->isWave32() ? AMDGPU::S_ANDN2_SAVEEXEC_B32 in optimizeOrSaveexecXorSequences()
H A DGCNCreateVOPD.cpp121 if (!AMDGPU::hasVOPD(*ST) || !ST->isWave32()) in runOnMachineFunction()
H A DSIRegisterInfo.cpp321 SpillSGPRToVGPR(EnableSpillSGPRToVGPR), isWave32(ST.isWave32()) { in SIRegisterInfo()
598 if (isWave32) { in getReservedRegs()
1674 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS); in spillSGPR()
1793 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS); in restoreSGPR()
1871 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, SGPR, false, 0, in spillEmergencySGPR()
2297 if (!isWave32) in eliminateFrameIndex()
2908 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass in getRegClassForSizeOnBank()
2933 return isWave32 ? AMDGPU::VCC_LO : AMDGPU::VCC; in getVCC()
2937 return isWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in getExec()
2952 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass in getRegClass()
H A DSIFrameLowering.cpp577 if (ST.isWave32()) { in emitEntryFunctionScratchRsrcRegSetup()
729 ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32 : AMDGPU::S_OR_SAVEEXEC_B64; in buildScratchExecCopy()
803 unsigned ExecMov = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in emitPrologue()
804 MCRegister Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in emitPrologue()
1071 unsigned ExecMov = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in emitEpilogue()
1072 MCRegister Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in emitEpilogue()
H A DGCNSubtarget.h938 return UserSGPRInit16Bug && isWave32(); in hasUserSGPRInit16Bug()
1239 bool isWave32() const { in isWave32() function
H A DGCNVOPDUtils.cpp182 if (!AMDGPU::hasVOPD(ST) || !ST.isWave32()) { in apply()
H A DSIInstrInfo.cpp1151 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in insertVectorSelect()
1165 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in insertVectorSelect()
1211 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in insertVectorSelect()
1229 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in insertVectorSelect()
2125 MI.setDesc(get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32 in expandPostRAPseudo()
5481 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in emitLoadSRsrcFromVGPRLoop()
5487 ST.isWave32() ? AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64; in emitLoadSRsrcFromVGPRLoop()
5600 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in loadSRsrcFromVGPR()
7745 if (!ST.isWave32()) in fixImplicitOperands()
8167 get(ST.isWave32() ? AMDGPU::S_MOV_B32_term in createPHISourceCopy()
[all …]
H A DVOPCInstructions.td205 let WaveSizePredicate = isWave32 in {
904 let WaveSizePredicate = isWave32 in
953 let WaveSizePredicate = isWave32 in
1209 let WaveSizePredicate = isWave32;
1223 let WaveSizePredicate = isWave32;
1241 let WaveSizePredicate = isWave32;
1255 let WaveSizePredicate = isWave32;
1303 let WaveSizePredicate = isWave32;
1319 let WaveSizePredicate = isWave32;
1340 let WaveSizePredicate = isWave32;
[all …]
H A DSILowerI1Copies.cpp420 return MRI.createVirtualRegister(ST.isWave32() ? &AMDGPU::SReg_32RegClass in createLaneMaskReg()
456 IsWave32 = ST->isWave32(); in runOnMachineFunction()
H A DVOPDInstructions.td71 let WaveSizePredicate = isWave32;
H A DSIPreEmitPeephole.cpp89 const bool IsWave32 = ST.isWave32(); in optimizeVccBranch()
H A DSIAnnotateControlFlow.cpp128 IntMask = ST.isWave32() ? Type::getInt32Ty(Context) in initialize()
H A DSIWholeQuadMode.cpp888 Register VCC = ST->isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC; in lowerKillF32()
1004 unsigned MovOpc = ST->isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in lowerKillI1()
1545 if (ST->isWave32()) { in runOnMachineFunction()
H A DSIShrinkInstructions.cpp723 Op->setReg(ST->isWave32() ? AMDGPU::SGPR_NULL : AMDGPU::SGPR_NULL64); in tryReplaceDeadSDST()
736 unsigned VCCReg = ST->isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC; in runOnMachineFunction()
H A DSILowerControlFlow.cpp706 bool IsWave32 = ST.isWave32(); in lowerInitExec()
852 if (ST.isWave32()) { in runOnMachineFunction()
H A DVOP2Instructions.td247 let WaveSizePredicate = isWave32 in {
313 let WaveSizePredicate = isWave32 in {
1204 let WaveSizePredicate = isWave32;
1229 let WaveSizePredicate = isWave32;
1479 let WaveSizePredicate = isWave32;
1506 let WaveSizePredicate = isWave32;
1531 let WaveSizePredicate = isWave32;
H A DAMDGPUAsmPrinter.cpp415 if (MF.getSubtarget<GCNSubtarget>().isWave32()) { in getAmdhsaKernelCodeProperties()
1053 if (STM.isWave32()) in EmitPALMetadata()
H A DSIOptimizeExecMaskingPreRA.cpp382 const bool Wave32 = ST.isWave32(); in runOnMachineFunction()
H A DAMDGPURegisterBankInfo.cpp770 Subtarget.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in executeInWaterfallLoop()
772 Subtarget.isWave32() ? AMDGPU::S_MOV_B32_term : AMDGPU::S_MOV_B64_term; in executeInWaterfallLoop()
774 const unsigned XorTermOpc = Subtarget.isWave32() ? in executeInWaterfallLoop()
776 const unsigned AndSaveExecOpc = Subtarget.isWave32() ? in executeInWaterfallLoop()
778 const unsigned ExecReg = Subtarget.isWave32() ? in executeInWaterfallLoop()
923 {LLT::scalar(Subtarget.isWave32() ? 32 : 64)}, in executeInWaterfallLoop()
H A DSIFixSGPRCopies.cpp615 TII->get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in runOnMachineFunction()
H A DSIInstrInfo.h1107 bool isWave32() const;
H A DSIInstructions.td297 let WaveSizePredicate = isWave32 in {
1833 let WaveSizePredicate = isWave32;
2218 let WaveSizePredicate = isWave32 in {
2255 } // end isWave32

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