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Searched refs:isShiftedMask (Results 1 – 10 of 10) sorted by relevance

/llvm-project-15.0.7/llvm/unittests/ADT/
H A DAPIntTest.cpp1747 TEST(APIntTest, isShiftedMask) { in TEST() argument
1748 EXPECT_FALSE(APInt(32, 0x01010101).isShiftedMask()); in TEST()
1749 EXPECT_TRUE(APInt(32, 0xf0000000).isShiftedMask()); in TEST()
1750 EXPECT_TRUE(APInt(32, 0xffff0000).isShiftedMask()); in TEST()
1751 EXPECT_TRUE(APInt(32, 0xff << 1).isShiftedMask()); in TEST()
1766 EXPECT_FALSE(APInt(N, 0).isShiftedMask()); in TEST()
1772 EXPECT_TRUE(MaskVal.isShiftedMask()); in TEST()
1773 EXPECT_TRUE(MaskVal.isShiftedMask(MaskIdx, MaskLen)); in TEST()
1779 EXPECT_TRUE(MaskVal.isShiftedMask()); in TEST()
1780 EXPECT_TRUE(MaskVal.isShiftedMask(MaskIdx, MaskLen)); in TEST()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/ADT/
H A DAPInt.h491 bool isShiftedMask() const { in isShiftedMask() function
503 bool isShiftedMask(unsigned &MaskIdx, unsigned &MaskLen) const { in isShiftedMask() function
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstCombineIntrinsic.cpp999 if (MaskC->getValue().isShiftedMask(MaskIdx, MaskLen)) { in instCombineIntrinsic()
1043 if (MaskC->getValue().isShiftedMask(MaskIdx, MaskLen)) { in instCombineIntrinsic()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp2555 static bool isShiftedMask(uint64_t Mask, EVT VT) { in isShiftedMask() function
2599 if (!isShiftedMask(Known.Zero.getZExtValue(), VT)) in tryBitfieldInsertOpFromOrAndImm()
2773 (isShiftedMask(Mask0Imm, VT) || isShiftedMask(Mask1Imm, VT))) { in tryBitfieldInsertOpFromOr()
2778 if (isShiftedMask(Mask0Imm, VT)) { in tryBitfieldInsertOpFromOr()
H A DAArch64ISelLowering.cpp13685 if (XorC->getAPIntValue().isShiftedMask(MaskIdx, MaskLen)) { in isDesirableToCommuteXorWithShift()
/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineAddSub.cpp976 C2->isNegative() && C2->isShiftedMask() && *C == (*C & *C2)) { in foldAddWithConstant()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp3155 if (Mask->getAPIntValue().isShiftedMask(MaskIdx, MaskLen) && in performSrlCombine()
/llvm-project-15.0.7/clang/lib/Sema/
H A DSemaChecking.cpp3972 if (Result.isShiftedMask() || (~Result).isShiftedMask()) in SemaValueIsRunOfOnes()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp13625 if (XorC->getAPIntValue().isShiftedMask(MaskIdx, MaskLen)) { in isDesirableToCommuteXorWithShift()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp12801 } else if (Mask.isShiftedMask(ShAmt, ActiveBits)) { in reduceLoadWidth()