| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsTargetMachine.cpp | 73 bool isLittle) { in computeDataLayout() argument
78 if (isLittle) in computeDataLayout()
125 bool isLittle) in MipsTargetMachine() argument
126 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, in MipsTargetMachine()
129 isLittle(isLittle), TLOF(std::make_unique<MipsTargetObjectFile>()), in MipsTargetMachine()
131 Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this, None), in MipsTargetMachine()
133 isLittle, *this, None), in MipsTargetMachine()
135 isLittle, *this, None) { in MipsTargetMachine()
203 TargetTriple, CPU, FS, isLittle, *this, in getSubtargetImpl()
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| H A D | MipsTargetMachine.h | 28 bool isLittle; variable
43 CodeGenOpt::Level OL, bool JIT, bool isLittle);
74 bool isLittleEndian() const { return isLittle; } in isLittleEndian()
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| H A D | MipsCallingConv.td | 135 CCIfSubtargetNot<"isLittle()",
172 CCIfSubtargetNot<"isLittle()",
204 CCIfSubtarget<"isLittle()",
206 CCIfSubtargetNot<"isLittle()",
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| H A D | MipsAsmPrinter.cpp | 591 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum; in PrintAsmOperand()
594 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1; in PrintAsmOperand()
642 if (Subtarget->isLittle()) in PrintAsmMemoryOperand()
646 if (!Subtarget->isLittle()) in PrintAsmMemoryOperand()
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| H A D | MipsSEFrameLowering.cpp | 324 if (!Subtarget.isLittle()) in expandBuildPairF64()
375 int64_t Offset = 4 * (Subtarget.isLittle() ? N : (1 - N)); in expandExtractElementF64()
467 if (!STI.isLittle()) in emitPrologue()
483 if (!STI.isLittle()) in emitPrologue()
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| H A D | MipsSubtarget.h | 284 bool isLittle() const { return IsLittle; } in isLittle() function
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| H A D | MipsISelDAGToDAG.cpp | 241 8, !Subtarget->isLittle())) in selectVecAddAsVecSubIfProfitable()
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| H A D | MipsCallLowering.cpp | 179 if (!STI.isLittle()) in assignCustomValue()
276 if (!STI.isLittle()) in assignCustomValue()
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| H A D | MipsISelLowering.cpp | 1791 if (Subtarget.isLittle()) { in emitAtomicBinaryPartword()
1978 if (Subtarget.isLittle()) { in emitAtomicCmpSwapPartword()
2691 bool IsLittle = Subtarget.isLittle(); in lowerLOAD()
2883 if (ArgFlags.isInReg() && !Subtarget.isLittle()) { in CC_MipsO32()
3308 if (!Subtarget.isLittle()) in LowerCall()
3708 if (!Subtarget.isLittle()) in LowerFormalArguments()
4458 if (isLittle) in passByValArg()
4770 const bool IsLittle = Subtarget.isLittle(); in emitLDR_W()
4816 const bool IsLittle = Subtarget.isLittle(); in emitLDR_D()
4900 const bool IsLittle = Subtarget.isLittle(); in emitSTR_W()
[all …]
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| H A D | MipsSEISelLowering.cpp | 609 bool IsLittleEndian = !Subtarget.isLittle(); in performORCombine()
853 EltSize, !Subtarget.isLittle()) || in performDSPShiftCombine()
1188 if (!Subtarget.isLittle()) in lowerLOAD()
1211 if (!Subtarget.isLittle()) in lowerSTORE()
1659 !Subtarget.isLittle()); in lowerINTRINSIC_WO_CHAIN()
1695 !Subtarget.isLittle()); in lowerINTRINSIC_WO_CHAIN()
2465 !Subtarget.isLittle()) && SplatBitSize <= 64) { in lowerBUILD_VECTOR()
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| H A D | MipsSEISelDAGToDAG.cpp | 526 MinSizeInBits, !Subtarget->isLittle())) in selectVSplat()
1102 !Subtarget->isLittle())) in trySelect()
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| H A D | MipsISelLowering.h | 585 const ISD::ArgFlagsTy &Flags, bool isLittle,
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| H A D | MipsExpandPseudo.cpp | 463 if (STI->isLittle()) { in expandAtomicBinOpSubword()
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| H A D | MipsFastISel.cpp | 1249 if (ArgSize < 8 && !Subtarget->isLittle()) in processCallArgs()
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| H A D | MipsInstrInfo.td | 236 def IsLE : Predicate<"Subtarget->isLittle()">;
237 def IsBE : Predicate<"!Subtarget->isLittle()">;
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMTargetMachine.h | 38 bool isLittle; variable
45 CodeGenOpt::Level OL, bool isLittle);
53 bool isLittleEndian() const { return isLittle; } in isLittleEndian()
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| H A D | ARMTargetMachine.cpp | 142 bool isLittle) { in computeDataLayout() argument
146 if (isLittle) in computeDataLayout()
221 CodeGenOpt::Level OL, bool isLittle) in ARMBaseTargetMachine() argument
222 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, in ARMBaseTargetMachine()
226 TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) { in ARMBaseTargetMachine()
300 I = std::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle, in getSubtargetImpl()
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| H A D | ARMCallLowering.cpp | 159 bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle(); in assignCustomValue()
336 bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle(); in assignCustomValue()
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| H A D | ARMSubtarget.h | 465 bool isLittle() const { return IsLittle; } in isLittle() function
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| H A D | ARMParallelDSP.cpp | 287 if (!ST->isLittle()) { in runOnFunction()
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| H A D | ARMISelLowering.cpp | 2204 if (!Subtarget->isLittle()) in LowerCallResult()
2221 if (!Subtarget->isLittle()) in LowerCallResult()
2292 unsigned id = Subtarget->isLittle() ? 0 : 1; in PassF64ArgInRegs()
3155 bool isLittleEndian = Subtarget->isLittle(); in LowerReturn()
4308 if (!Subtarget->isLittle()) in GetF64FormalArgument()
13938 if (!Subtarget->isLittle()) in PerformMVEVMULLCombine()
14875 if (!Subtarget->isLittle() && BVSwap) in PerformVMOVRRDCombine()
14893 if (!Subtarget->isLittle() && BVSwap) in PerformVMOVRRDCombine()
15178 if (ST->isLittle()) in PerformVECTOR_REG_CASTCombine()
21201 if (!Subtarget->isLittle()) in emitLoadLinked()
[all …]
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| H A D | ARMExpandPseudoInsts.cpp | 1427 if (STI->isLittle()) { in CMSESaveClearFPRegsV8()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetMachine.h | 65 bool isLittle;
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| H A D | AArch64TargetMachine.cpp | 319 TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) { in AArch64TargetMachine()
433 *this, isLittle, MinSVEVectorSize, in getSubtargetImpl()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 734 bool isLittle() const { return IsLittleEndian; } in isLittle() function in __anon03c4d4620211::MipsAsmParser
4406 if (isLittle()) in expandUlh()
4456 if (isLittle()) in expandUsh()
4497 if (isLittle()) in expandUxw()
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