| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | RDFDeadCode.cpp | 61 if (MI->hasOrderedMemoryRef() || MI->hasUnmodeledSideEffects() || in isLiveInstr()
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| H A D | HexagonStoreWidening.cpp | 275 if (MI->hasOrderedMemoryRef() || instrAliased(Group, MI)) in createStoreGroup()
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| H A D | HexagonExpandCondsets.cpp | 833 bool Ordered = TheI.hasOrderedMemoryRef(); in canMoveMemTo()
843 if (Ordered && MI->hasOrderedMemoryRef()) in canMoveMemTo()
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| H A D | HexagonVLIWPacketizer.cpp | 1522 bool OrdRefs = I.hasOrderedMemoryRef() || J.hasOrderedMemoryRef(); in isLegalToPacketizeTogether()
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| H A D | HexagonInstrInfo.cpp | 1980 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
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| /llvm-project-15.0.7/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 94 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIOptimizeExecMaskingPreRA.cpp | 440 I->hasUnmodeledSideEffects() || I->hasOrderedMemoryRef()) in runOnMachineFunction()
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| H A D | SILoadStoreOptimizer.cpp | 2156 if (MI.hasOrderedMemoryRef() || MI.hasUnmodeledSideEffects()) { in collectMergeableInsts()
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| H A D | SIInstrInfo.cpp | 3172 if (MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LoadStoreOpt.cpp | 286 return MI.hasUnmodeledSideEffects() || MI.hasOrderedMemoryRef(); in isInstHardMergeHazard()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64LoadStoreOptimizer.cpp | 1284 if (MI.hasOrderedMemoryRef() || TII->isLdStPairSuppressed(MI)) in areCandidatesToMergeOrPair()
1288 assert(!FirstMI.hasOrderedMemoryRef() && in areCandidatesToMergeOrPair()
2063 if (MI.hasOrderedMemoryRef()) in tryToPromoteLoadFromStore()
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| H A D | AArch64InstrInfo.cpp | 1055 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
2480 if (MI.hasOrderedMemoryRef()) in isCandidateToMergeOrPair()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsDelaySlotFiller.cpp | 467 if (MI.hasOrderedMemoryRef() && (OrigSeenLoad || OrigSeenStore)) { in hasHazard()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyRegStackify.cpp | 180 } else if (MI.hasOrderedMemoryRef()) { in query()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 712 (MI.hasOrderedMemoryRef() && in isDependenceBarrier()
2293 SI->hasOrderedMemoryRef() || DI->hasOrderedMemoryRef()) in isLoopCarriedDep()
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| H A D | MachineInstr.cpp | 1192 (mayLoad() && hasOrderedMemoryRef())) { in isSafeToMove()
1329 bool MachineInstr::hasOrderedMemoryRef() const { in hasOrderedMemoryRef() function in MachineInstr
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| H A D | ScheduleDAGInstrs.cpp | 535 (MI->hasOrderedMemoryRef() && !MI->isDereferenceableInvariantLoad()); in isGlobalMemoryObject()
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| H A D | MachineSink.cpp | 1195 if (I.isCall() || I.hasOrderedMemoryRef()) { in hasStoreBetween()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 1191 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstr.h | 1611 bool hasOrderedMemoryRef() const;
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2779 if (LdSt.hasOrderedMemoryRef() || LdSt.getNumExplicitOperands() != 3) in isLdStSafeToCluster()
5546 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
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