Searched refs:getWavefrontSize (Results 1 – 20 of 20) sorted by relevance
200 unsigned getWavefrontSize() const { in getWavefrontSize() function
322 const unsigned WaveSize = getWavefrontSize(); in getOccupancyWithLocalMemSize()366 return std::make_pair(1, getWavefrontSize()); in getDefaultFlatWorkGroupSize()567 return getWavefrontSize() == 32 ? AMDGPUDwarfFlavour::Wave32 in getAMDGPUDwarfFlavour()
1240 return getWavefrontSize() == 32; in isWave32()1244 return getWavefrontSize() == 64; in isWave64()
82 if (ST->getWavefrontSize() == 64) { in requiresWorkAroundForInst()93 assert(ST->getWavefrontSize() == 32); in requiresWorkAroundForInst()
501 Type *const WaveTy = B.getIntNTy(ST->getWavefrontSize()); in optimizeAtomic()553 Value *const LastLaneIdx = B.getInt32(ST->getWavefrontSize() - 1); in optimizeAtomic()
291 unsigned WaveSize = ST.getWavefrontSize(); in haveFreeLanesForSGPRSpill()308 unsigned WaveSize = ST.getWavefrontSize(); in allocateSGPRSpillToVGPR()
209 HSACodeProps.mWavefrontSize = STM.getWavefrontSize(); in getHSACodeProps()885 Kern.getDocument()->getNode(STM.getWavefrontSize()); in getHSAKernelProps()
707 STM.getMaxWaveScratchSize() / STM.getWavefrontSize(); in getSIProgramInfo()901 ProgInfo.ScratchSize * STM.getWavefrontSize(), 1ULL << ScratchAlignShift); in getSIProgramInfo()
99 ST->getWavefrontSize(); in isLaneMaskReg()
748 const unsigned WavefrontSize = ST.getWavefrontSize(); in lowerInitExec()
400 return ST.enableFlatScratch() ? 1 : ST.getWavefrontSize(); in getScratchScaleFactor()
1330 unsigned N = ST.getWavefrontSize(); in fold_wavefrontsize()
1143 if (MRI->getType(Dst).getSizeInBits() != STI.getWavefrontSize()) in selectIntrinsicIcmp()1184 if (Size != STI.getWavefrontSize()) in selectBallot()1523 if (WGSize <= STI.getWavefrontSize()) { in selectSBarrier()
9 def isWave32 : Predicate<"Subtarget->getWavefrontSize() == 32">,11 def isWave64 : Predicate<"Subtarget->getWavefrontSize() == 64">,
4894 unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize(); in lowerICMPIntrinsic()4925 unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize(); in lowerFCMPIntrinsic()6935 return DAG.getConstant(MF.getSubtarget<GCNSubtarget>().getWavefrontSize(), in LowerINTRINSIC_WO_CHAIN()8012 if (WGSize <= ST.getWavefrontSize()) in LowerINTRINSIC_VOID()12840 return Subtarget->getWavefrontSize() == 64 ? &AMDGPU::SReg_64RegClass in getRegClassFor()12926 return hasCFUser(V, Visited, Subtarget->getWavefrontSize()); in requiresUniformRegister()
1423 Offset *= ST.getWavefrontSize(); in buildSpillLoadStore()
6533 unsigned Opcode = (ST.getWavefrontSize() == 64) ? AMDGPU::S_CSELECT_B64 in lowerSelect()7379 uint64_t IndexStride = ST.getWavefrontSize() == 64 ? 3 : 2; in getScratchRsrcWords23()
5715 B.buildConstant(MI.getOperand(0), ST.getWavefrontSize()); in legalizeIntrinsic()
181 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
650 unsigned getWavefrontSize(const MCSubtargetInfo *STI) { in getWavefrontSize() function721 return divideCeil(FlatWorkGroupSize, getWavefrontSize(STI)); in getWavesPerWorkGroup()