| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86RegisterInfo.h | 66 getSubClassWithSubReg(const TargetRegisterClass *RC,
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| H A D | X86RegisterInfo.cpp | 85 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, in getSubClassWithSubReg() function in X86RegisterInfo
93 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx); in getSubClassWithSubReg()
102 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi); in getMatchingSuperRegClass()
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| H A D | X86InstructionSelector.cpp | 759 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubIdx); in selectTruncOrPtrToInt()
1176 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubIdx); in emitExtractSubreg()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.h | 63 getSubClassWithSubReg(const TargetRegisterClass *RC,
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| H A D | AArch64RegisterInfo.cpp | 168 AArch64RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, in getSubClassWithSubReg() function in AArch64RegisterInfo
177 return AArch64GenRegisterInfo::getSubClassWithSubReg(RC, Idx); in getSubClassWithSubReg()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 453 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
466 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx); in ConstrainForSubReg()
573 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); in EmitSubregNode()
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| H A D | FastISel.cpp | 2107 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx)); in fastEmitInst_extractsubreg()
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| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.h | 381 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const { in getSubClassWithSubReg() function
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| H A D | CodeGenRegisters.cpp | 1041 CodeGenRegisterClass *BiggestSuperRegRC = getSubClassWithSubReg(SubIdx); in getMatchingSubClassWithSubRegs()
1598 if (RegClass.getSubClassWithSubReg(&SubRegIndex) == nullptr) in computeSubRegLaneMasks()
2293 if (RC->getSubClassWithSubReg(&SubIdx) != RC) in inferMatchingSuperRegClass()
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| H A D | CodeGenTarget.cpp | 373 CodeGenRegisterClass *SubClassWithSubReg = RC.getSubClassWithSubReg(SubIdx); in getSuperRegForSubReg()
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| H A D | RegisterInfoEmitter.cpp | 1530 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx)) in runTargetDesc()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 624 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { in getSubClassWithSubReg() function
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TargetRegisterInfo.cpp | 533 if (getSubClassWithSubReg(RC, Idx) != RC) in getCoveringSubRegIndexes()
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| H A D | PeepholeOptimizer.cpp | 478 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
488 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr; in INITIALIZE_PASS_DEPENDENCY()
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| H A D | MachineInstr.cpp | 913 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx); in getRegClassConstraintEffect()
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| H A D | MachineVerifier.cpp | 2125 TRI->getSubClassWithSubReg(RC, SubIdx); in visitMachineOperand()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 511 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubReg); in selectG_EXTRACT()
595 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubRegs[I]); in selectG_UNMERGE_VALUES()
768 Src0RC = TRI.getSubClassWithSubReg(Src0RC, SubReg); in selectG_INSERT()
2024 = TRI.getSubClassWithSubReg(SrcRC, SubRegIdx); in selectG_TRUNC()
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| H A D | AMDGPUISelDAGToDAG.cpp | 396 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC, in getOperandRegClass()
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| H A D | SIInstrInfo.cpp | 5437 const TargetRegisterClass *OpRC = RI.getSubClassWithSubReg( in legalizeGenericOperand()
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