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Searched refs:getSpillSize (Results 1 – 25 of 41) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreMachineFunctionInfo.cpp50 LRSpillSlot = MFI.CreateFixedObject(TRI.getSpillSize(RC), 0, true); in createLRSpillSlot()
52 LRSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC), in createLRSpillSlot()
67 MFI.CreateStackObject(TRI.getSpillSize(RC), TRI.getSpillAlign(RC), true); in createFPSpillSlot()
79 unsigned Size = TRI.getSpillSize(RC); in createEHSpillSlot()
H A DXCoreFrameLowering.cpp577 unsigned Size = TRI.getSpillSize(RC); in processFunctionBeforeFrameFinalized()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsMachineFunction.cpp164 I = MF.getFrameInfo().CreateStackObject(TRI.getSpillSize(RC), in createEhDataRegsFI()
178 I = MF.getFrameInfo().CreateStackObject(TRI.getSpillSize(RC), in createISRRegFI()
205 TRI.getSpillSize(*RC), TRI.getSpillAlign(*RC), false); in getMoveF64ViaSpillFI()
H A DMipsFrameLowering.cpp127 unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R)); in estimateStackSize()
H A DMipsSEFrameLowering.cpp894 int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC), in determineCalleeSaves()
910 int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC), in determineCalleeSaves()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86LowerTileCopy.cpp90 unsigned Size = TRI->getSpillSize(X86::TILERegClass); in runOnMachineFunction()
94 Size = TRI->getSpillSize(X86::GR64RegClass); in runOnMachineFunction()
H A DX86FastPreTileConfig.cpp128 unsigned Size = TRI->getSpillSize(RC); in getStackSpaceFor()
H A DX86InstrInfo.cpp3573 switch (STI.getRegisterInfo()->getSpillSize(*RC)) { in getLoadStoreRegOpcode()
3858 assert(MFI.getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) && in storeRegToStackSlot()
3880 unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16); in storeRegToStackSlot()
3897 assert(MFI.getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) && in loadRegFromStackSlot()
3920 unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16); in loadRegFromStackSlot()
6803 unsigned SpillSize = STI.getRegisterInfo()->getSpillSize(*RC); in getBroadcastOpcode()
6897 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16); in unfoldMemoryOperand()
6974 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*DstRC), 16); in unfoldMemoryOperand()
7041 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16); in unfoldMemoryOperand()
7107 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16); in unfoldMemoryOperand()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCInstrInfo.cpp309 assert(TRI->getSpillSize(*RC) == 4 && in storeRegToStackSlot()
336 assert(TRI->getSpillSize(*RC) == 4 && in loadRegFromStackSlot()
H A DARCFrameLowering.cpp442 int RegScavFI = MFI.CreateStackObject(RegInfo->getSpillSize(*RC), in processFunctionBeforeFrameFinalized()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIMachineFunctionInfo.cpp483 TRI.getSpillSize(*RC), TRI.getSpillAlign(*RC)); in allocateWWMReservedSpillSlots()
493 TRI.getSpillSize(AMDGPU::SGPR_32RegClass), 0, false); in getScavengeFI()
496 TRI.getSpillSize(AMDGPU::SGPR_32RegClass), in getScavengeFI()
H A DSILowerSGPRSpills.cpp222 int JunkFI = MFI.CreateStackObject(TRI->getSpillSize(*RC), in spillCalleeSavedRegs()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonVExtract.cpp146 int FI = MFI.CreateStackObject(HRI.getSpillSize(VecRC), Alignment, in runOnMachineFunction()
H A DHexagonFrameLowering.cpp1704 int FI = MFI.CreateFixedSpillStackObject(TRI->getSpillSize(*RC), S->Offset); in assignCalleeSavedSpillSlots()
1716 unsigned Size = TRI->getSpillSize(*RC); in assignCalleeSavedSpillSlots()
1941 unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass); in expandStoreVec2()
1993 unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass); in expandLoadVec2()
2171 unsigned S = HRI.getSpillSize(*RC); in determineCalleeSaves()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DStackMaps.cpp255 Locs.emplace_back(Location::Register, TRI->getSpillSize(*RC), in parseOperand()
341 unsigned Size = TRI->getSpillSize(*TRI->getMinimalPhysRegClass(Reg)); in createLiveOutReg()
H A DTargetInstrInfo.cpp393 Size = TRI->getSpillSize(*RC); in getStackSlotRange()
409 assert(TRI->getSpillSize(*RC) >= (Offset + Size) && "bad subregister range"); in getStackSlotRange()
412 Offset = TRI->getSpillSize(*RC) - (Offset + Size); in getStackSlotRange()
H A DFixupStatepointCallerSaved.cpp94 return TRI.getSpillSize(*RC); in getRegisterSize()
H A DVirtRegMap.cpp96 unsigned Size = TRI->getSpillSize(*RC); in createSpillSlot()
H A DRegisterScavenging.cpp452 unsigned NeedSize = TRI->getSpillSize(RC); in spill()
H A DTargetLoweringBase.cpp1266 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC)) in findRepresentativeClass()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h283 unsigned getSpillSize(const TargetRegisterClass &RC) const { in getSpillSize() function
H A DMachineInstr.h1642 Optional<unsigned> getSpillSize(const TargetInstrInfo *TII) const;
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZFrameLowering.cpp230 unsigned Size = TRI->getSpillSize(*RC); in assignCalleeSavedSpillSlots()
1034 unsigned Size = TRI->getSpillSize(*RC); in assignCalleeSavedSpillSlots()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYFrameLowering.cpp441 unsigned size = TRI->getSpillSize(*RC); in determineCalleeSaves()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVFrameLowering.cpp1035 RegInfo->getSpillSize(*RC), RegInfo->getSpillAlign(*RC), false)); in processFunctionBeforeFrameFinalized()

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