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Searched refs:getSimpleVT (Results 1 – 25 of 72) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp885 MVT SimpleVT = LoadedVT.getSimpleVT(); in tryLoad()
1019 MVT SimpleVT = LoadedVT.getSimpleVT(); in tryLoadVector()
1072 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLoadVector()
1099 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLoadVector()
1316 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLDGLDU()
1327 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLDGLDU()
1339 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLDGLDU()
1348 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLDGLDU()
1739 MVT SimpleVT = StoreVT.getSimpleVT(); in tryStore()
1897 MVT ScalarVT = StoreVT.getSimpleVT().getScalarType(); in tryStoreVector()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DValueTypes.h95 return getSimpleVT().changeVectorElementTypeToInteger(); in changeVectorElementTypeToInteger()
105 return getSimpleVT().changeVectorElementType(EltVT.getSimpleVT()); in changeVectorElementType()
118 return getSimpleVT().changeTypeToInteger(); in changeTypeToInteger()
288 MVT getSimpleVT() const { in getSimpleVT() function
H A DTargetLowering.h580 MVT LoadMVT = LoadVT.getSimpleVT(); in isLoadBitCastBeneficial()
1099 return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op]; in getOperationAction()
1280 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy; in getLoadExtAction()
1281 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy; in getLoadExtAction()
1305 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy; in getTruncStoreAction()
1306 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy; in getTruncStoreAction()
1504 return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
1521 assert((unsigned)VT.getSimpleVT().SimpleTy < in getRegisterType()
1523 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy]; in getRegisterType()
1554 assert((unsigned)VT.getSimpleVT().SimpleTy <
[all …]
H A DTargetCallingConv.h215 VT = vt.getSimpleVT(); in InputArg()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp247 MVT VT = RealVT.getSimpleVT(); in getRegForValue()
479 VT.getSimpleVT()); in selectBinaryOp()
525 Register ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), in selectBinaryOp()
1399 Register ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), in selectCast()
1416 MVT SrcVT = SrcEVT.getSimpleVT(); in selectBitCast()
1417 MVT DstVT = DstEVT.getSimpleVT(); in selectBitCast()
1448 MVT Ty = ETy.getSimpleVT(); in selectFreeze()
1607 Register ResultReg = fastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), ISD::FNEG, in selectFNeg()
1622 Register IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), in selectFNeg()
1633 ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST, in selectFNeg()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVVPISelLowering.cpp61 auto Packing = getTypePacking(LegalVecVT.getSimpleVT()); in lowerToVVP()
153 Packing, DataVT.getVectorElementType().getSimpleVT()); in lowerVVP_LOAD_STORE()
181 MVT DataVT = getIdiomaticVectorType(Op.getNode())->getSimpleVT(); in splitPackedLoadStore()
268 getLegalVectorType(Packing, DataVT.getVectorElementType().getSimpleVT()); in lowerVVP_GATHER_SCATTER()
314 MVT DataVT = getIdiomaticVectorType(Op.getNode())->getSimpleVT(); in legalizeInternalLoadStoreOp()
410 MVT IdiomVT = getIdiomaticVectorType(Op.getNode())->getSimpleVT(); in legalizePackedAVL()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp530 LoadConversionTbl, ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT())) in getCastInstrCost()
553 DstTy.getSimpleVT(), SrcTy.getSimpleVT())) in getCastInstrCost()
565 DstTy.getSimpleVT(), SrcTy.getSimpleVT())) in getCastInstrCost()
582 SrcTy.getSimpleVT(), DstTy.getSimpleVT())) in getCastInstrCost()
593 SrcTy.getSimpleVT(), DstTy.getSimpleVT())) in getCastInstrCost()
619 DstTy.getSimpleVT(), in getCastInstrCost()
620 SrcTy.getSimpleVT())) { in getCastInstrCost()
730 DstTy.getSimpleVT(), in getCastInstrCost()
731 SrcTy.getSimpleVT())) in getCastInstrCost()
760 DstTy.getSimpleVT(), in getCastInstrCost()
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H A DARMFastISel.cpp629 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant()
676 VT = evt.getSimpleVT(); in isTypeLegal()
1342 MVT SrcVT = SrcEVT.getSimpleVT(); in ARMEmitCmp()
1537 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIToFP()
1779 MVT VT = FPVT.getSimpleVT(); in SelectBinaryFPOp()
2127 MVT RVVT = RVEVT.getSimpleVT(); in SelectRet()
2192 return ARMMaterializeGV(GV, LCREVT.getSimpleVT()); in getLibcallReg()
2759 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIntExt()
2760 MVT DestVT = DestEVT.getSimpleVT(); in SelectIntExt()
3045 switch (ArgVT.getSimpleVT().SimpleTy) { in fastLowerArguments()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp304 switch (VT.getSimpleVT().SimpleTy) { in isValidIndexedLoad()
327 MVT VT = LD->getMemoryVT().getSimpleVT(); in tryIndexedLoad()
356 MVT VT = LD->getMemoryVT().getSimpleVT(); in tryIndexedBinOp()
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dshuffle-combine-crash-3.ll7 ; llc: ../include/llvm/CodeGen/ValueTypes.h:251: llvm::MVT llvm::EVT::getSimpleVT() const: Assert…
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelDAGToDAG.cpp107 MVT VT = cast<MemSDNode>(Op)->getMemoryVT().getSimpleVT(); in SelectAddr()
124 MVT VT = LD->getMemoryVT().getSimpleVT(); in selectIndexedLoad()
368 MVT VT = LD->getMemoryVT().getSimpleVT(); in select()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp448 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant()
596 VT = evt.getSimpleVT(); in isTypeLegal()
1365 switch (ArgVT.getSimpleVT().SimpleTy) { in fastLowerArguments()
1734 MVT RVVT = RVEVT.getSimpleVT(); in selectRet()
1813 MVT SrcVT = SrcEVT.getSimpleVT(); in selectIntExt()
1814 MVT DestVT = DestEVT.getSimpleVT(); in selectIntExt()
1914 MVT DestVT = DestEVT.getSimpleVT(); in selectDivRem()
1975 MVT Op0MVT = TLI.getValueType(DL, Op0->getType(), true).getSimpleVT(); in selectShift()
2091 MVT VMVT = TLI.getValueType(DL, V->getType(), true).getSimpleVT(); in getRegEnsuringSimpleIntegerWidening()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp81 switch (LoadedVT.getSimpleVT().SimpleTy) { in SelectIndexedLoad()
477 switch (StoredVT.getSimpleVT().SimpleTy) { in SelectIndexedStore()
771 MVT ResTy = N->getValueType(0).getSimpleVT(); in SelectVAlign()
834 MVT OpTy = Op.getValueType().getSimpleVT(); in SelectTypecast()
841 MVT ResTy = N->getValueType(0).getSimpleVT(); in SelectP2D()
849 MVT ResTy = N->getValueType(0).getSimpleVT(); in SelectD2P()
858 MVT ResTy = N->getValueType(0).getSimpleVT(); in SelectV2Q()
860 MVT OpTy = N->getOperand(0).getValueType().getSimpleVT(); (void)OpTy; in SelectV2Q()
872 MVT ResTy = N->getValueType(0).getSimpleVT(); in SelectQ2V()
1170 if (!OpVT.isSimple() || OpVT.getSimpleVT() != MVT::i1) in ppHoistZextI1()
[all …]
H A DHexagonISelLowering.h384 return Op.getValueType().getSimpleVT(); in ty()
387 return { Ops.first.getValueType().getSimpleVT(), in ty()
388 Ops.second.getValueType().getSimpleVT() }; in ty()
H A DHexagonISelDAGToDAGHVX.cpp671 : InpNode(Inp), InpTy(Inp->getValueType(0).getSimpleVT()) {} in ResultStack()
1072 MVT OpTy = Op.getValueType().getSimpleVT(); in materialize()
1665 MVT LegalTy = Lower.getTypeToTransformTo(Ctx, ElemTy).getSimpleVT(); in scalarizeShuffle()
2272 MVT ResTy = N->getValueType(0).getSimpleVT(); in selectShuffle()
2344 MVT Ty = N->getValueType(0).getSimpleVT(); in selectRor()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FastISel.cpp298 VT = evt.getSimpleVT(); in isTypeLegal()
493 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitStore()
665 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitStore()
704 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src); in X86FastEmitExtend()
1261 SrcReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, SrcReg); in X86SelectRet()
1359 switch (VT.getSimpleVT().SimpleTy) { in X86ChooseCmpOpcode()
1382 switch (VT.getSimpleVT().SimpleTy) { in X86ChooseCmpImmediateOpcode()
1585 ResultReg = fastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::ZERO_EXTEND, in X86SelectZExt()
2437 MVT DstVT = TLI.getValueType(DL, I->getType()).getSimpleVT(); in X86SelectIntToFP()
3078 switch (ArgVT.getSimpleVT().SimpleTy) { in fastLowerArguments()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp952 MVT SVT = VT.getSimpleVT(); in getTypeConversion()
1041 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); in getTypeConversion()
1064 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); in getTypeConversion()
1549 RegisterVT = RegisterEVT.getSimpleVT(); in getVectorTypeBreakdown()
1862 MVT VT = MTy.isSimple() ? MTy.getSimpleVT() : MVT::i64; in getTypeLegalizationCost()
1867 return std::make_pair(Cost, MTy.getSimpleVT()); in getTypeLegalizationCost()
1874 return std::make_pair(Cost, MTy.getSimpleVT()); in getTypeLegalizationCost()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp321 TLI->getAsmOperandValueType(DL, OpTy, true).getSimpleVT(); in lowerInlineAsm()
331 TLI->getAsmOperandValueType(DL, Call.getType()).getSimpleVT(); in lowerInlineAsm()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp275 VT = Evt.getSimpleVT(); in isTypeLegal()
825 MVT SrcVT = SrcEVT.getSimpleVT(); in PPCEmitCmp()
1077 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIToFP()
1754 MVT RVVT = RVEVT.getSimpleVT(); in SelectRet()
1918 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIntExt()
1919 MVT DestVT = DestEVT.getSimpleVT(); in SelectIntExt()
2254 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant()
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dhvx-isel-vselect-v256i16.ll3 ; "llvm::MVT llvm::EVT::getSimpleVT() const: Assertion `isSimple() &&
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFrameLowering.cpp83 FuncInfo->addLocal(ValueVT.getSimpleVT()); in getLocalForStackObject()
H A DWebAssemblyFastISel.cpp121 return VT.isSimple() ? VT.getSimpleVT().SimpleTy in getSimpleType()
1171 Register Reg = fastEmit_ISD_BITCAST_r(VT.getSimpleVT(), RetVT.getSimpleVT(), in selectBitCast()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp445 MTy.getSimpleVT())) in getIntrinsicInstrCost()
1839 DstTy.getSimpleVT(), in getCastInstrCost()
1840 SrcTy.getSimpleVT())) in getCastInstrCost()
1870 FP16Tbl, ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT())) in getCastInstrCost()
2171 SelCondTy.getSimpleVT(), in getCmpSelInstrCost()
2172 SelValTy.getSimpleVT())) in getCmpSelInstrCost()
2807 CostTableLookup(ShuffleTbl, TTI::SK_Splice, PromotedVT.getSimpleVT()); in getSpliceCost()
H A DAArch64FastISel.cpp516 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant()
967 VT = evt.getSimpleVT(); in isTypeLegal()
1453 MVT VT = EVT.getSimpleVT(); in emitCmp()
2856 emitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed); in selectIntToFP()
2915 MVT VT = ArgVT.getSimpleVT().SimpleTy; in fastLowerArguments()
3828 MVT RVVT = RVEVT.getSimpleVT(); in selectRet()
3879 MVT SrcVT = SrcEVT.getSimpleVT(); in selectTrunc()
3880 MVT DestVT = DestEVT.getSimpleVT(); in selectTrunc()
4536 MVT DestVT = DestEVT.getSimpleVT(); in selectRem()
4885 IdxN = emitIntExt(IdxVT.getSimpleVT(), IdxN, PtrVT, /*isZExt=*/false); in getRegForGEPIndex()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp524 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCallArguments()
527 << (unsigned)RegVT.getSimpleVT().SimpleTy << "\n"); in LowerCallArguments()

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