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Searched refs:getMatchingSuperReg (Results 1 – 25 of 34) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIMachineFunctionInfo.cpp219 ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addPrivateSegmentBuffer()
226 ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchPtr()
233 ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addQueuePtr()
241 = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addKernargSegmentPtr()
248 ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchID()
255 ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addFlatScratchInit()
262 ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addImplicitBufferPtr()
H A DR600ControlFlowFinalizer.cpp280 DstMI = TRI->getMatchingSuperReg(Reg, in isCompatibleWithClause()
289 SrcMI = TRI->getMatchingSuperReg(Reg, in isCompatibleWithClause()
H A DSIRegisterInfo.cpp542 return getMatchingSuperReg(BaseReg, AMDGPU::sub0, &AMDGPU::SGPR_128RegClass); in reservedPrivateSegmentBufferReg()
3022 if (MCPhysReg Super = getMatchingSuperReg(Reg, AMDGPU::lo16, &RC)) in get32BitRegister()
3025 if (MCPhysReg Super = getMatchingSuperReg(Reg, AMDGPU::hi16, in get32BitRegister()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp197 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM2RegisterClass()
217 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM4RegisterClass()
237 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM8RegisterClass()
/llvm-project-15.0.7/llvm/lib/MC/
H A DMCRegisterInfo.cpp24 MCRegisterInfo::getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg() function in MCRegisterInfo
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h588 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg() function
590 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); in getMatchingSuperReg()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVMCInstLower.cpp188 Reg = TRI->getMatchingSuperReg(Reg, RISCV::sub_16, &RISCV::FPR32RegClass); in lowerRISCVVMachineInstrToMCInst()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DCalcSpillWeights.cpp74 return TRI.getMatchingSuperReg(CopiedPReg, Sub, RC); in copyHint()
H A DTwoAddressInstructionPass.cpp1511 assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB)) in processTiedPairs()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZShortenInst.cpp89 TRI->getMatchingSuperReg(Reg, thisSubRegIdx, &SystemZ::GR64BitRegClass); in shortenIIF()
H A DSystemZInstrInfo.cpp806 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64), in copyPhysReg()
809 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64), in copyPhysReg()
820 RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_h64), in copyPhysReg()
823 RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_l64), in copyPhysReg()
H A DSystemZRegisterInfo.cpp117 PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(), in getRegAllocationHints()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMFrameLowering.cpp1768 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1787 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1802 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1900 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Restores()
1918 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Restores()
1931 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Restores()
H A DA15SDOptimizer.cpp145 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, in getDPRLaneFromSPR()
H A DARMBaseInstrInfo.cpp1707 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0, in expandPostRAPseudo()
1709 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0, in expandPostRAPseudo()
5055 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
5062 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
5366 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0, in getPartialRegUpdateClearance()
/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCRegisterInfo.h465 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx,
/llvm-project-15.0.7/llvm/lib/Target/AVR/AsmParser/
H A DAVRAsmParser.cpp83 return MRI->getMatchingSuperReg(Reg, From, Class); in toDREG()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp500 Opd.setReg(getRegisterInfo().getMatchingSuperReg( in ExpandCCR()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonCopyToCombine.cpp595 unsigned DoubleRegDest = TRI->getMatchingSuperReg(LoRegDef, SubLo, SuperRC); in combine()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp3449 MCRegister DestRegX = TRI->getMatchingSuperReg( in copyPhysReg()
3451 MCRegister SrcRegX = TRI->getMatchingSuperReg( in copyPhysReg()
3475 MCRegister DestRegX = TRI->getMatchingSuperReg( in copyPhysReg()
3477 MCRegister SrcRegX = TRI->getMatchingSuperReg( in copyPhysReg()
3688 RI.getMatchingSuperReg(DestReg, AArch64::hsub, &AArch64::FPR32RegClass); in copyPhysReg()
3690 RI.getMatchingSuperReg(SrcReg, AArch64::hsub, &AArch64::FPR32RegClass); in copyPhysReg()
3699 RI.getMatchingSuperReg(DestReg, AArch64::bsub, &AArch64::FPR32RegClass); in copyPhysReg()
3701 RI.getMatchingSuperReg(SrcReg, AArch64::bsub, &AArch64::FPR32RegClass); in copyPhysReg()
4541 TRI.getMatchingSuperReg(SrcReg, SpillSubreg, SpillRC)) { in foldMemoryOperandImpl()
H A DAArch64LoadStoreOptimizer.cpp1128 IsStoreXReg ? Register(TRI->getMatchingSuperReg( in promoteLoadFromStore()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp924 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, in convertMIMGInst()
941 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, in convertMIMGInst()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp3511 DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm, in copyPhysReg()
3513 SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, in copyPhysReg()
3526 DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm, in copyPhysReg()
3528 SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, in copyPhysReg()
4831 DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass); in expandNOVLXLoad()
4854 SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass); in expandNOVLXStore()
4923 TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass); in expandPostRAPseudo()
4943 TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass); in expandPostRAPseudo()
/llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp273 NewReg = MCOperand::createReg(MRI.getMatchingSuperReg( in printInst()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp1405 Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC); in printVectorList()

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